Samsung Starts Mass Production of 9th Generation V-NAND: 1Tb 3D TLC NAND
Samsung Electronics has started mass production of its 9th generation of V-NAND memory. The first dies based on their latest NAND tech come in a 1 Tb capacity using a triple-level cell (TLC) architecture, with data transfer rates as high as 3.2 GT/s. The new 3D TLC NAND memory will initially be used to build high-capacity and high-performance SSDs, which will help to solidify Samsung's position in the storage market.
Diving right in, Samsung is conspicuously avoiding to list the number of layers in their latest generation NAND, which is the principle driving factor in increasing capacity generation-on-generation. The company's current 8th gen V-NAND is 236 layers – similar to its major competitors – and word on the street is that 9th gen V-NAND ups that to 290 layers, though this remains to be confirmed.
Regardless, Samsung says that its 9th generation V-NAND memory boasts an approximate 50% improvement in bit density over its 8th generation predecessor. Driving this gains, the company cites the miniaturization of the cell size, as well as the integration of enhanced memory cell technologies that reduce interference and extend the lifespan of the cells. With their latest NAND technology, Samsung has also been able to eliminate dummy channel holes, thus reducing the planar area of the memory cells.
Interestingly, today's announcement also marks the first time that Samsung has publicly confirmed their use of string stacking in their NAND, referring to it as their "double-stack structure." The company is widely believed to have been using sting stacking back in their 8th generation NAND as well, however this was never confirmed by the company. Regardless, the use of string stacking is only going to increase from here, as vendors look to keep adding layers to their NAND dies, while manufacturing variability and channel hole tolerances make it difficult to produce more than 150-200 layers in a single stack.
| Samsung TLC V- NAND Flash Memory | ||
| 9th Gen V-NAND | 8th Gen V-NAND | |
| Layers | 290? | 236 |
| Decks | 2 (x145) | 2 (x118) |
| Die Capacity | 1 Tbit | 1 Tbit |
| Die Size (mm2) | ?mm2 | ?mm2 |
| Density (Gbit/mm2) | ? | ? |
| I/O Speed | 3.2 GT/s (Toggle 5.1) |
2.4 GT/s (Toggle 5.0) |
| Planes | 6? | 4 |
| CuA / PuC | Yes | Yes |
Speaking of channel holes, another key technological enhancement in the 9th gen V-NAND is Samsung's advanced 'channel hole etching' technology. This process improves manufacturing productivity by enabling the simultaneous creation of electron pathways within a double-stack structure. This method is crucial as it enables efficient drilling through more layers, which is increasingly important as cell layers are added.
The latest V-NAND also features the introduction of a faster NAND flash interface, Toggle DDR 5.1, which boosts peak data transfer rates by 33% to 3.2 GT/s, or almost 400MB/sec for a single die. Additionally, 9th gen V-NAND's power consumption has been reduced by 10%, according to Samsung. Though Samsung doesn't state under what conditions – presumably, this is at iso-frequency rather than max frequency.
Samsung's launch of 1Tb TLC V-NAND is set to be followed by the release of a quad-level cell (QLC) model later this year.
"We are excited to deliver the industry’s first 9th-gen V-NAND which will bring future... SSDs
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PCI-SIG Demonstrates PCIe 6.0 Interoperability at FMS 2024 As the deployment of PCIe 5.0 picks up steam in both datacenter and consumer markets, PCI-SIG is not sitting idle, and is already working on getting the ecosystem ready for the updats to the PCIe specifications. At FMS 2024, some vendors were even talking about PCIe 7.0 with its 128 GT/s capabilities despite PCIe 6.0 not even starting to ship yet. We caught up with PCI-SIG to get some updates on its activities and have a discussion on the current state of the PCIe ecosystem. PCI-SIG has already made the PCIe 7.0 specifications (v 0.5) available to its members, and expects full specifications to be officially released sometime in 2025. The goal is to deliver a 128 GT/s data rate with up to 512 GBps of bidirectional traffic using x16 links. Similar to PCIe 6.0, this specification will also utilize PAM4 signaling and maintain backwards compatibility. Power efficiency as well as silicon die area are also being kept in mind as part of the drafting process. The move to PAM4 signaling brings higher bit-error rates compared to the previous NRZ scheme. This made it necessary to adopt a different error correction scheme in PCIe 6.0 - instead of operating on variable length packets, PCIe 6.0's Flow Control Unit (FLIT) encoding operates on fixed size packets to aid in forward error correction. PCIe 7.0 retains these aspects. The integrators list for the PCIe 6.0 compliance program is also expected to come out in 2025, though initial testing is already in progress. This was evident by the FMS 2024 demo involving Cadence's 3nm test chip for its PCIe 6.0 IP offering along with Teledyne Lecroy's PCIe 6.0 analyzer. These timelines track well with the specification completion dates and compliance program availability for previous PCIe generations. We also received an update on the optical workgroup - while being optical-technology agnostic, the WG also intends to develop technology-specific form-factors including pluggable optical transceivers, on-board optics, co-packaged optics, and optical I/O. The logical and electrical layers of the PCIe 6.0 specifications are being enhanced to accommodate the new optical PCIe standardization and this process will also be done with PCIe 7.0 to coincide with that standard's release next year. The PCI-SIG also has ongoing cabling initiatives. On the consumer side, we have seen significant traction for Thunderbolt and external GPU enclosures. However, even datacenters and enterprise systems are moving towards cabling solutions as it becomes evident that disaggregation of components such as storage from the CPU and GPU are better for thermal design. Additionally maintaining signal integrity over longer distances becomes difficult for on-board signal traces. Cabling internal to the computing systems can help here. OCuLink emerged as a good candidate and was adopted fairly widely as an internal link in server systems. It has even made an appearance in mini-PCs from some Chinese manufacturers in its external avatar for the consumer market, albeit with limited traction. As speeds increase, a widely-adopted standard for external PCIe peripherals (or even connecting components within a system) will become imperative. Storage
The Cougar Poseidon Ultra 360 ARGB AIO Cooler Review: Bright Lights, Average Cooling Cougar, established in 2008, has become a notable name in the PC hardware market, particularly among gamers and enthusiasts. While Cougar might appear to be a relatively recent addition to the industry, it is backed by HEC/Compucase, a veteran in the PC market known primarily for its OEM products. Cougar was created as a subsidiary to focus on developing and marketing high-performance products tailored to the needs of gamers and PC enthusiasts. Initially, Cougar focused primarily on PC cases, gradually expanding its product lineup as the brand gained recognition. Over the years, Cougar has successfully diversified its offerings to include a wide range of products, from gaming chairs to mechanical keyboards. This strategic expansion has allowed Cougar to establish a strong presence in the gaming hardware market. In this review, we are focusing on Cougar's latest entry into the liquid cooling market, the Poseidon Ultra 360 ARGB cooler. The Poseidon Ultra 360 ARGB is a high-performance, all-in-one liquid cooler featuring a 360mm radiator and vibrant ARGB lighting, designed to appeal to both performance enthusiasts and those looking for a visually striking setup. This review will delve into the AIO cooler’s key features, cooling efficiency, and noise levels, to determine how it stands up against the competition in the increasingly crowded liquid cooler market. Cases/Cooling/PSUs
G.Skill Intros Low Latency DDR5 Memory Modules: CL30 at 6400 MT/s G.Skill on Tuesday introduced its ultra-low-latency DDR5-6400 memory modules that feature a CAS latency of 30 clocks, which appears to be the industry's most aggressive timings yet for DDR5-6400 sticks. The modules will be available for both AMD and Intel CPU-based systems. With every new generation of DDR memory comes an increase in data transfer rates and an extension of relative latencies. While for the vast majority of applications, the increased bandwidth offsets the performance impact of higher timings, there are applications that favor low latencies. However, shrinking latencies is sometimes harder than increasing data transfer rates, which is why low-latency modules are rare. Nonetheless, G.Skill has apparently managed to cherry-pick enough DDR5 memory chips and build appropriate printed circuit boards to produce DDR5-6400 modules with CL30 timings, which are substantially lower than the CL46 timings recommended by JEDEC for this speed bin. This means that while JEDEC-standard modules have an absolute latency of 14.375 ns, G.Skill's modules can boast a latency of just 9.375 ns – an approximately 35% decrease. G.Skill's DDR5-6400 CL30 39-39-102 modules have a capacity of 16 GB and will be available in 32 GB dual-channel kits, though the company does not disclose voltages, which are likely considerably higher than those standardized by JEDEC. The company plans to make its DDR5-6400 modules available both for AMD systems with EXPO profiles (Trident Z5 Neo RGB and Trident Z5 Royal Neo) and for Intel-powered PCs with XMP 3.0 profiles (Trident Z5 RGB and Trident Z5 Royal). For AMD AM5 systems that have a practical limitation of 6000 MT/s – 6400 MT/s for DDR5 memory (as this is roughly as fast as AMD's Infinity Fabric can operate at with a 1:1 ratio), the new modules will be particularly beneficial for AMD's Ryzen 7000 and Ryzen 9000-series processors. G.Skill notes that since its modules are non-standard, they will not work with all systems but will operate on high-end motherboards with properly cooled CPUs. The new ultra-low-latency memory kits will be available worldwide from G.Skill's partners starting in late August 2024. The company did not disclose the pricing of these modules, but since we are talking about premium products that boast unique specifications, they are likely to be priced accordingly. Memory
MediaTek to Add NVIDIA G-Sync Support to Monitor Scalers, Make G-Sync Displays More Accessible
NVIDIA on Tuesday said that future monitor scalers from MediaTek will support its G-Sync technologies. NVIDIA is partnering with MediaTek to integrate its full range of G-Sync technologies into future monitors without requiring a standalone G-Sync module, which makes advanced gaming features more accessible across a broader range of displays.
Traditionally, G-Sync technology relied on a dedicated G-sync module – based on an Altera FPGA – to handle syncing display refresh rates with the GPU in order to reduce screen tearing, stutter, and input lag. As a more basic solution, in 2019 NVIDIA introduced G-Sync Compatible certification and branding, which leveraged the industry-standard VESA AdaptiveSync technology to handle variable refresh rates. In lieu of using a dedicated module, leveraging AdaptiveSync allowed for cheaper monitors, with NVIDIA's program serving as a stamp of approval that the monitor worked with NVIDIA GPUs and met NVIDIA's performance requirements. Still, G-Sync Compatible monitors still lack some features that, to date, require the dedicated G-Sync module.
Through this new partnership with MediaTek, MediaTek will bring support for all of NVIDIA's G-Sync technologies, including the latest G-Sync Pulsar, directly into their scalers. G-Sync Pulsar enhances motion clarity and reduces ghosting, providing a smoother gaming experience. In addition to variable refresh rates and Pulsar, MediaTek-based G-Sync displays will support such features as variable overdrive, 12-bit color, Ultra Low Motion Blur, low latency HDR, and Reflex Analyzer. This integration will allow more monitors to support a full range of G-Sync features without having to incorporate an expensive FPGA.
The first monitors to feature full G-Sync support without needing an NVIDIA module include the AOC Agon Pro AG276QSG2, Acer Predator XB273U F5, and ASUS ROG Swift 360Hz PG27AQNR. These monitors offer 360Hz refresh rates, 1440p resolution, and HDR support.
What remains to be seen is which specific MediaTek's scalers will support NVIDIA's G-Sync technology – or if the company is going to implement support into all of their scalers going forward. It also remains to be seen whether monitors with NVIDIA's dedicated G-Sync modules retain any advantages over displays with MediaTek's scalers.
Monitors
MediaTek to Add NVIDIA G-Sync Support to Monitor Scalers, Make G-Sync Displays More Accessible
NVIDIA on Tuesday said that future monitor scalers from MediaTek will support its G-Sync technologies. NVIDIA is partnering with MediaTek to integrate its full range of G-Sync technologies into future monitors without requiring a standalone G-Sync module, which makes advanced gaming features more accessible across a broader range of displays.
Traditionally, G-Sync technology relied on a dedicated G-sync module – based on an Altera FPGA – to handle syncing display refresh rates with the GPU in order to reduce screen tearing, stutter, and input lag. As a more basic solution, in 2019 NVIDIA introduced G-Sync Compatible certification and branding, which leveraged the industry-standard VESA AdaptiveSync technology to handle variable refresh rates. In lieu of using a dedicated module, leveraging AdaptiveSync allowed for cheaper monitors, with NVIDIA's program serving as a stamp of approval that the monitor worked with NVIDIA GPUs and met NVIDIA's performance requirements. Still, G-Sync Compatible monitors still lack some features that, to date, require the dedicated G-Sync module.
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Microchip Demonstrates Flashtec 5016 Enterprise SSD Controller
Microchip recently announced the availability of their second PCIe Gen 5 enterprise SSD controller - the Flashtec 5016. Like the 4016, this is also a 16-channel controller, but there are some key updates:
- PCIe 5.0 lane organization: Operation in x4 or dual independent x2 / x2 mode in the 5016, compared to the x8, or x4, or dual independent x4 / x2 mode in the 4016.
- DRAM support: Four ranks of DDR5-5200 in the 5016, compared to two ranks of DDR4-3200 in the 4016.
- Extended NAND support: 2400 MT/s NAND in the 4016, compared to the 3200 MT/s NAND support in the 5016.
- Performance improvements: The 5016 is capable of delivering 3.5M+ random read IOPS compared to the 3M+ of the 4016.
Microchip's enterprise SSD controllers provide a high level of flexibility to SSD vendors by providing them with significant horsepower and accelerators. The 5016 includes Cortex-A53 cores for SSD vendors to run custom applications relevant to SSD management. However, compared to the Gen4 controllers, there are two additional cores in the CPU cluster. The DRAM subsystem includes ECC support (both out-of-band and inline, as desired by the SSD vendor).
At FMS 2024, the company demonstrated an application of the neural network engines embedded in the Gen5 controllers. Controllers usually employ a 'read-retry' operation with altered read-out voltages for flash reads that do not complete successfully. Microchip implemented a machine learning approach to determine the read-out voltage based on the health history of the NAND block using the NN engines in the controller. This approach delivers tangible benefits for read latency and power consumption (thanks to a smaller number of errors on the first read).
The 4016 and 5016 come with a single-chip root of trust implementation for hardware security. A secure boot process with dual-signature authentication ensures that the controller firmware is not maliciously altered in the field. The company also brought out the advantages of their controller's implementation of SR-IOV, flexible data placement, and zoned namespaces along with their 'credit engine' scheme for multi-tenant cloud workloads. These aspects were also brought out in other demonstrations.
Microchip's press release included quotes from the usual NAND vendors - Solidigm, Kioxia, and Micron. On the customer front, Longsys has been using Flashtec controllers in their enterprise offerings along with YMTC NAND. It is likely that this collaboration will continue further using the new 5016 controller.
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G.Skill Intros Low Latency DDR5 Memory Modules: CL30 at 6400 MT/s
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G.Skill's DDR5-6400 CL30 39-39-102 modules have a capacity of 16 GB and will be available in 32 GB dual-channel kits, though the company does not disclose voltages, which are likely considerably higher than those standardized by JEDEC.
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G.Skill notes that since its modules are non-standard, they will not work with all systems but will operate on high-end motherboards with properly cooled CPUs.
The new ultra-low-latency memory kits will be available worldwide from G.Skill's partners starting in late August 2024. The company did not disclose the pricing of these modules, but since we are talking about premium products that boast unique specifications, they are likely to be priced accordingly.
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Silicon Motion Demonstrates Flexible Data Placement on MonTitan Gen 5 Enterprise SSD Platform
At FMS 2024, the technological requirements from the storage and memory subsystem took center stage. Both SSD and controller vendors had various demonstrations touting their suitability for different stages of the AI data pipeline - ingestion, preparation, training, checkpointing, and inference. Vendors like Solidigm have different types of SSDs optimized for different stages of the pipeline. At the same time, controller vendors have taken advantage of one of the features introduced recently in the NVM Express standard - Flexible Data Placement (FDP).
FDP involves the host providing information / hints about the areas where the controller could place the incoming write data in order to reduce the write amplification. These hints are generated based on specific block sizes advertised by the device. The feature is completely backwards-compatible, with non-FDP hosts working just as before with FDP-enabled SSDs, and vice-versa.
Silicon Motion's MonTitan Gen 5 Enterprise SSD Platform was announced back in 2022. Since then, Silicon Motion has been touting the flexibility of the platform, allowing its customers to incorporate their own features as part of the customization process. This approach is common in the enterprise space, as we have seen with Marvell's Bravera SC5 SSD controller in the DapuStor SSDs and Microchip's Flashtec controllers in the Longsys FORESEE enterprise SSDs.
At FMS 2024, the company was demonstrating the advantages of flexible data placement by allowing a single QLC SSD based on their MonTitan platform to take part in different stages of the AI data pipeline while maintaining the required quality of service (minimum bandwidth) for each process. The company even has a trademarked name (PerformaShape) for the firmware feature in the controller that allows the isolation of different concurrent SSD accesses (from different stages in the AI data pipeline) to guarantee this QoS. Silicon Motion claims that this scheme will enable its customers to get the maximum write performance possible from QLC SSDs without negatively impacting the performance of other types of accesses.
Silicon Motion and Phison have market leadership in the client SSD controller market with similar approaches. However, their enterprise SSD controller marketing couldn't be more different. While Phison has gone in for a turnkey solution with their Gen 5 SSD platform (to the extent of not adopting the white label route for this generation, and instead opting to get the SSDs qualified with different cloud service providers themselves), Silicon Motion is opting for a different approach. The flexibility and customization possibilities can make platforms like the MonTitan appeal to flash array vendors.
Storage![Rapidus Wants to Offer Fully Automated Packaging for 2nm Fab to Cut Chip Lead Times <p align="center"><a href="https://www.anandtech.com/show/21525/rapidus-2nm-fully-automated-chip-packaging-to-cut-lead-times"><img src="https://images.anandtech.com/doci/21525/intel-foundry-wafer-semiconductor-fab-ifs-678_575px.jpg" alt="" /></a></p><p><p>One of the core challenges that Rapidus will face when it kicks off volume production of chips on its 2nm-class process technology in 2027 is lining up customers. With Intel, Samsung, and TSMC all slated to offer their own 2nm-class nodes by that time, Rapidus will need some kind of advantage to attract customers away from its more established rivals. To that end, the company thinks they've found their edge: fully automated packaging that will allow for shorter chip lead times than manned packaging operations.</p>
<p>In an interview with <a href="https://asia.nikkei.com/Editor-s-Picks/Interview/Japan-s-Rapidus-to-fully-automate-2-nm-chip-fab-president-says">Nikkei</a>, Rapidus' president, Atsuyoshi Koike, outlined the company's vision to use advanced packaging as a competitive edge for the new fab. <a href="https://www.anandtech.com/show/21411/rapidus-adds-chip-packaging-services-to-plans-for-32b-2nm-fab">The Hokkaido facility</a>, which is currently under construction and is expecting to begin equipment installation this December, is already slated to both produce chips and offer advanced packaging services within the same facility, an industry first. But ultimately, Rapidus biggest plan to differentiate itself is by automating the back-end fab processes (chip packaging) to provide significantly faster turnaround times.</p>
<p>Rapidus is targetting back-end production in particular as, compared to front-end (lithography) production, back-end production still heavily relies on human labor. No other advanced packaging fab has fully automated the process thus far, which provides for a degree of flexibility, but slows throughput. But with automation in place to handle this aspect of chip production, Rapidus would be able to increase chip packaging efficiency and speed, which is crucial as chip assembly tasks become more complex. Rapidus is also collaborating with multiple Japanese suppliers to source materials for back-end production. </p>
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<p>Due to its lack of track record and experience of chip production as. well as limited visibility for success, Rapidus is finding it difficult to attract private financing. The company is in discussions with the government to make it easier to raise capital, including potential loan guarantees, and is hopeful that new legislation will assist in this effort.</p>
</p> Semiconductors](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tRrsI94Ga02x7y9VB5K4u2nkCzOOts1i5A3P2WrraPdS7SwASdzvdV1oL3gB_vJgL4JlT0-hs12-uM91EAH7GC_VEFOrq4sHKKK_B7Wh0h8npHPFFXAqlQ0u6yUFba7LevO1b23q8lh0yhD3VG-sXmiUcdtLHUQRYFiIoIcogeo0rz=w72-h72-p-k-no-nu)
Rapidus Wants to Offer Fully Automated Packaging for 2nm Fab to Cut Chip Lead Times
![](https://twitter.com/share?url=https://compbuddey.blogspot.com/2024/04/samsung-starts-mass-production-of-9th_28.html&text=Samsung Starts Mass Production of 9th Generation V-NAND: 1Tb 3D TLC NAND <p align="center"><a href="https://www.anandtech.com/show/21365/samsung-starts-mass-production-of-9th-generation-vnand-1tb-3d-tlc-nand"><img src="https://images.anandtech.com/doci/21365/9th-Generation-V-NAND_main1_575px.jpg" alt="" /></a></p><p><p>Samsung Electronics has started mass production of its 9th generation of V-NAND memory. The first dies based on their latest NAND tech come in a 1 Tb capacity using a triple-level cell (TLC) architecture, with data transfer rates as high as 3.2 GT/s. The new 3D TLC NAND memory will initially be used to build high-capacity and high-performance SSDs, which will help to solidify Samsung's position in the storage market.</p>
<p>Diving right in, Samsung is conspicuously avoiding to list the number of layers in their latest generation NAND, which is the principle driving factor in increasing capacity generation-on-generation. The company's current 8th gen V-NAND is 236 layers – similar to its major competitors – and word on the street is that 9th gen V-NAND ups that to 290 layers, though this remains to be confirmed.</p>
<p>Regardless, Samsung says that its 9th generation V-NAND memory boasts an approximate 50% improvement in bit density over its 8th generation predecessor. Driving this gains, the company cites the miniaturization of the cell size, as well as the integration of enhanced memory cell technologies that reduce interference and extend the lifespan of the cells. With their latest NAND technology, Samsung has also been able to eliminate dummy channel holes, thus reducing the planar area of the memory cells.</p>
<p>Interestingly, today's announcement also marks the first time that Samsung has publicly confirmed their use of string stacking in their NAND, referring to it as their "double-stack structure." The company is widely believed to have been using sting stacking back in their 8th generation NAND as well, however this was never confirmed by the company. Regardless, the use of string stacking is only going to increase from here, as vendors look to keep adding layers to their NAND dies, while manufacturing variability and channel hole tolerances make it difficult to produce more than 150-200 layers in a single stack.</p>
<table border="1" cellpadding="1" cellspacing="1" width="70%">
<tbody>
<tr class="tgrey">
<td align="center" colspan="3">Samsung TLC V- NAND Flash Memory</td>
</tr>
<tr class="tlblue">
<td class="tlgrey" colspan="1" rowspan="1"> </td>
<td align="center" rowspan="1">9th Gen V-NAND</td>
<td align="center" colspan="1" rowspan="1">8th Gen V-NAND</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">Layers</td>
<td align="center">290?</td>
<td align="center">236</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">Decks</td>
<td align="center">2 (x145)</td>
<td align="center">2 (x118)</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">Die Capacity</td>
<td align="center" rowspan="1">1 Tbit</td>
<td align="center" rowspan="1">1 Tbit</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">Die Size (mm<sup>2</sup>)</td>
<td align="center" rowspan="1">?mm2</td>
<td align="center" rowspan="1">?mm2</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">Density (Gbit/mm<sup>2</sup>)</td>
<td align="center" rowspan="1">?</td>
<td align="center" rowspan="1">?</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">I/O Speed</td>
<td align="center" rowspan="1">3.2 GT/s<br />
(Toggle 5.1)</td>
<td align="center" rowspan="1">2.4 GT/s<br />
(Toggle 5.0)</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">Planes</td>
<td align="center">6?</td>
<td align="center">4</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">CuA / PuC</td>
<td align="center">Yes</td>
<td align="center">Yes</td>
</tr>
</tbody>
</table>
<p>Speaking of channel holes, another key technological enhancement in the 9th gen V-NAND is Samsung's advanced 'channel hole etching' technology. This process improves manufacturing productivity by enabling the simultaneous creation of electron pathways within a double-stack structure. This method is crucial as it enables efficient drilling through more layers, which is increasingly important as cell layers are added.</p>
<p>The latest V-NAND also features the introduction of a faster NAND flash interface, Toggle DDR 5.1, which boosts peak data transfer rates by 33% to 3.2 GT/s, or almost 400MB/sec for a single die. Additionally, 9th gen V-NAND's power consumption has been reduced by 10%, according to Samsung. Though Samsung doesn't state under what conditions – presumably, this is at iso-frequency rather than max frequency.</p>
<p>Samsung's launch of 1Tb TLC V-NAND is set to be followed by the release of a quad-level cell (QLC) model later this year.</p>
<p>"We are excited to deliver the industry’s first 9th-gen V-NAND which will bring future... SSDs){kind=link}
![](https://www.pinterest.com/pin/create/button/?url=https://compbuddey.blogspot.com/2024/04/samsung-starts-mass-production-of-9th_28.html&media=https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_ufNuFkw1WVhfxjaD3LAu1AamdhWPbgJ9P3UfBVT71qLPCF0JNSN2VQWhoEcwVh0_ACtS3XukvfEy5C3PHp-jWCYuEIgUVmGPgy5mCSijSKYzeLtSMvp_g6ADrnP6SxPyRculDTnWKBo-N5v8WJp-GP&description=Samsung Starts Mass Production of 9th Generation V-NAND: 1Tb 3D TLC NAND <p align="center"><a href="https://www.anandtech.com/show/21365/samsung-starts-mass-production-of-9th-generation-vnand-1tb-3d-tlc-nand"><img src="https://images.anandtech.com/doci/21365/9th-Generation-V-NAND_main1_575px.jpg" alt="" /></a></p><p><p>Samsung Electronics has started mass production of its 9th generation of V-NAND memory. The first dies based on their latest NAND tech come in a 1 Tb capacity using a triple-level cell (TLC) architecture, with data transfer rates as high as 3.2 GT/s. The new 3D TLC NAND memory will initially be used to build high-capacity and high-performance SSDs, which will help to solidify Samsung's position in the storage market.</p>
<p>Diving right in, Samsung is conspicuously avoiding to list the number of layers in their latest generation NAND, which is the principle driving factor in increasing capacity generation-on-generation. The company's current 8th gen V-NAND is 236 layers – similar to its major competitors – and word on the street is that 9th gen V-NAND ups that to 290 layers, though this remains to be confirmed.</p>
<p>Regardless, Samsung says that its 9th generation V-NAND memory boasts an approximate 50% improvement in bit density over its 8th generation predecessor. Driving this gains, the company cites the miniaturization of the cell size, as well as the integration of enhanced memory cell technologies that reduce interference and extend the lifespan of the cells. With their latest NAND technology, Samsung has also been able to eliminate dummy channel holes, thus reducing the planar area of the memory cells.</p>
<p>Interestingly, today's announcement also marks the first time that Samsung has publicly confirmed their use of string stacking in their NAND, referring to it as their "double-stack structure." The company is widely believed to have been using sting stacking back in their 8th generation NAND as well, however this was never confirmed by the company. Regardless, the use of string stacking is only going to increase from here, as vendors look to keep adding layers to their NAND dies, while manufacturing variability and channel hole tolerances make it difficult to produce more than 150-200 layers in a single stack.</p>
<table border="1" cellpadding="1" cellspacing="1" width="70%">
<tbody>
<tr class="tgrey">
<td align="center" colspan="3">Samsung TLC V- NAND Flash Memory</td>
</tr>
<tr class="tlblue">
<td class="tlgrey" colspan="1" rowspan="1"> </td>
<td align="center" rowspan="1">9th Gen V-NAND</td>
<td align="center" colspan="1" rowspan="1">8th Gen V-NAND</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">Layers</td>
<td align="center">290?</td>
<td align="center">236</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">Decks</td>
<td align="center">2 (x145)</td>
<td align="center">2 (x118)</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">Die Capacity</td>
<td align="center" rowspan="1">1 Tbit</td>
<td align="center" rowspan="1">1 Tbit</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">Die Size (mm<sup>2</sup>)</td>
<td align="center" rowspan="1">?mm2</td>
<td align="center" rowspan="1">?mm2</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">Density (Gbit/mm<sup>2</sup>)</td>
<td align="center" rowspan="1">?</td>
<td align="center" rowspan="1">?</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">I/O Speed</td>
<td align="center" rowspan="1">3.2 GT/s<br />
(Toggle 5.1)</td>
<td align="center" rowspan="1">2.4 GT/s<br />
(Toggle 5.0)</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">Planes</td>
<td align="center">6?</td>
<td align="center">4</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">CuA / PuC</td>
<td align="center">Yes</td>
<td align="center">Yes</td>
</tr>
</tbody>
</table>
<p>Speaking of channel holes, another key technological enhancement in the 9th gen V-NAND is Samsung's advanced 'channel hole etching' technology. This process improves manufacturing productivity by enabling the simultaneous creation of electron pathways within a double-stack structure. This method is crucial as it enables efficient drilling through more layers, which is increasingly important as cell layers are added.</p>
<p>The latest V-NAND also features the introduction of a faster NAND flash interface, Toggle DDR 5.1, which boosts peak data transfer rates by 33% to 3.2 GT/s, or almost 400MB/sec for a single die. Additionally, 9th gen V-NAND's power consumption has been reduced by 10%, according to Samsung. Though Samsung doesn't state under what conditions – presumably, this is at iso-frequency rather than max frequency.</p>
<p>Samsung's launch of 1Tb TLC V-NAND is set to be followed by the release of a quad-level cell (QLC) model later this year.</p>
<p>"We are excited to deliver the industry’s first 9th-gen V-NAND which will bring future... SSDs){kind=link}
![](https://web.whatsapp.com/send?text=Samsung Starts Mass Production of 9th Generation V-NAND: 1Tb 3D TLC NAND <p align="center"><a href="https://www.anandtech.com/show/21365/samsung-starts-mass-production-of-9th-generation-vnand-1tb-3d-tlc-nand"><img src="https://images.anandtech.com/doci/21365/9th-Generation-V-NAND_main1_575px.jpg" alt="" /></a></p><p><p>Samsung Electronics has started mass production of its 9th generation of V-NAND memory. The first dies based on their latest NAND tech come in a 1 Tb capacity using a triple-level cell (TLC) architecture, with data transfer rates as high as 3.2 GT/s. The new 3D TLC NAND memory will initially be used to build high-capacity and high-performance SSDs, which will help to solidify Samsung's position in the storage market.</p>
<p>Diving right in, Samsung is conspicuously avoiding to list the number of layers in their latest generation NAND, which is the principle driving factor in increasing capacity generation-on-generation. The company's current 8th gen V-NAND is 236 layers – similar to its major competitors – and word on the street is that 9th gen V-NAND ups that to 290 layers, though this remains to be confirmed.</p>
<p>Regardless, Samsung says that its 9th generation V-NAND memory boasts an approximate 50% improvement in bit density over its 8th generation predecessor. Driving this gains, the company cites the miniaturization of the cell size, as well as the integration of enhanced memory cell technologies that reduce interference and extend the lifespan of the cells. With their latest NAND technology, Samsung has also been able to eliminate dummy channel holes, thus reducing the planar area of the memory cells.</p>
<p>Interestingly, today's announcement also marks the first time that Samsung has publicly confirmed their use of string stacking in their NAND, referring to it as their "double-stack structure." The company is widely believed to have been using sting stacking back in their 8th generation NAND as well, however this was never confirmed by the company. Regardless, the use of string stacking is only going to increase from here, as vendors look to keep adding layers to their NAND dies, while manufacturing variability and channel hole tolerances make it difficult to produce more than 150-200 layers in a single stack.</p>
<table border="1" cellpadding="1" cellspacing="1" width="70%">
<tbody>
<tr class="tgrey">
<td align="center" colspan="3">Samsung TLC V- NAND Flash Memory</td>
</tr>
<tr class="tlblue">
<td class="tlgrey" colspan="1" rowspan="1"> </td>
<td align="center" rowspan="1">9th Gen V-NAND</td>
<td align="center" colspan="1" rowspan="1">8th Gen V-NAND</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">Layers</td>
<td align="center">290?</td>
<td align="center">236</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">Decks</td>
<td align="center">2 (x145)</td>
<td align="center">2 (x118)</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">Die Capacity</td>
<td align="center" rowspan="1">1 Tbit</td>
<td align="center" rowspan="1">1 Tbit</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">Die Size (mm<sup>2</sup>)</td>
<td align="center" rowspan="1">?mm2</td>
<td align="center" rowspan="1">?mm2</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">Density (Gbit/mm<sup>2</sup>)</td>
<td align="center" rowspan="1">?</td>
<td align="center" rowspan="1">?</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">I/O Speed</td>
<td align="center" rowspan="1">3.2 GT/s<br />
(Toggle 5.1)</td>
<td align="center" rowspan="1">2.4 GT/s<br />
(Toggle 5.0)</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">Planes</td>
<td align="center">6?</td>
<td align="center">4</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">CuA / PuC</td>
<td align="center">Yes</td>
<td align="center">Yes</td>
</tr>
</tbody>
</table>
<p>Speaking of channel holes, another key technological enhancement in the 9th gen V-NAND is Samsung's advanced 'channel hole etching' technology. This process improves manufacturing productivity by enabling the simultaneous creation of electron pathways within a double-stack structure. This method is crucial as it enables efficient drilling through more layers, which is increasingly important as cell layers are added.</p>
<p>The latest V-NAND also features the introduction of a faster NAND flash interface, Toggle DDR 5.1, which boosts peak data transfer rates by 33% to 3.2 GT/s, or almost 400MB/sec for a single die. Additionally, 9th gen V-NAND's power consumption has been reduced by 10%, according to Samsung. Though Samsung doesn't state under what conditions – presumably, this is at iso-frequency rather than max frequency.</p>
<p>Samsung's launch of 1Tb TLC V-NAND is set to be followed by the release of a quad-level cell (QLC) model later this year.</p>
<p>"We are excited to deliver the industry’s first 9th-gen V-NAND which will bring future... SSDs | https://compbuddey.blogspot.com/2024/04/samsung-starts-mass-production-of-9th_28.html){kind=link}
![](mailto:?subject=Samsung Starts Mass Production of 9th Generation V-NAND: 1Tb 3D TLC NAND <p align="center"><a href="https://www.anandtech.com/show/21365/samsung-starts-mass-production-of-9th-generation-vnand-1tb-3d-tlc-nand"><img src="https://images.anandtech.com/doci/21365/9th-Generation-V-NAND_main1_575px.jpg" alt="" /></a></p><p><p>Samsung Electronics has started mass production of its 9th generation of V-NAND memory. The first dies based on their latest NAND tech come in a 1 Tb capacity using a triple-level cell (TLC) architecture, with data transfer rates as high as 3.2 GT/s. The new 3D TLC NAND memory will initially be used to build high-capacity and high-performance SSDs, which will help to solidify Samsung's position in the storage market.</p>
<p>Diving right in, Samsung is conspicuously avoiding to list the number of layers in their latest generation NAND, which is the principle driving factor in increasing capacity generation-on-generation. The company's current 8th gen V-NAND is 236 layers – similar to its major competitors – and word on the street is that 9th gen V-NAND ups that to 290 layers, though this remains to be confirmed.</p>
<p>Regardless, Samsung says that its 9th generation V-NAND memory boasts an approximate 50% improvement in bit density over its 8th generation predecessor. Driving this gains, the company cites the miniaturization of the cell size, as well as the integration of enhanced memory cell technologies that reduce interference and extend the lifespan of the cells. With their latest NAND technology, Samsung has also been able to eliminate dummy channel holes, thus reducing the planar area of the memory cells.</p>
<p>Interestingly, today's announcement also marks the first time that Samsung has publicly confirmed their use of string stacking in their NAND, referring to it as their "double-stack structure." The company is widely believed to have been using sting stacking back in their 8th generation NAND as well, however this was never confirmed by the company. Regardless, the use of string stacking is only going to increase from here, as vendors look to keep adding layers to their NAND dies, while manufacturing variability and channel hole tolerances make it difficult to produce more than 150-200 layers in a single stack.</p>
<table border="1" cellpadding="1" cellspacing="1" width="70%">
<tbody>
<tr class="tgrey">
<td align="center" colspan="3">Samsung TLC V- NAND Flash Memory</td>
</tr>
<tr class="tlblue">
<td class="tlgrey" colspan="1" rowspan="1"> </td>
<td align="center" rowspan="1">9th Gen V-NAND</td>
<td align="center" colspan="1" rowspan="1">8th Gen V-NAND</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">Layers</td>
<td align="center">290?</td>
<td align="center">236</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">Decks</td>
<td align="center">2 (x145)</td>
<td align="center">2 (x118)</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">Die Capacity</td>
<td align="center" rowspan="1">1 Tbit</td>
<td align="center" rowspan="1">1 Tbit</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">Die Size (mm<sup>2</sup>)</td>
<td align="center" rowspan="1">?mm2</td>
<td align="center" rowspan="1">?mm2</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">Density (Gbit/mm<sup>2</sup>)</td>
<td align="center" rowspan="1">?</td>
<td align="center" rowspan="1">?</td>
</tr>
<tr>
<td class="tlgrey" colspan="1" rowspan="1">I/O Speed</td>
<td align="center" rowspan="1">3.2 GT/s<br />
(Toggle 5.1)</td>
<td align="center" rowspan="1">2.4 GT/s<br />
(Toggle 5.0)</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">Planes</td>
<td align="center">6?</td>
<td align="center">4</td>
</tr>
<tr>
<td class="tlgrey" colspan="1">CuA / PuC</td>
<td align="center">Yes</td>
<td align="center">Yes</td>
</tr>
</tbody>
</table>
<p>Speaking of channel holes, another key technological enhancement in the 9th gen V-NAND is Samsung's advanced 'channel hole etching' technology. This process improves manufacturing productivity by enabling the simultaneous creation of electron pathways within a double-stack structure. This method is crucial as it enables efficient drilling through more layers, which is increasingly important as cell layers are added.</p>
<p>The latest V-NAND also features the introduction of a faster NAND flash interface, Toggle DDR 5.1, which boosts peak data transfer rates by 33% to 3.2 GT/s, or almost 400MB/sec for a single die. Additionally, 9th gen V-NAND's power consumption has been reduced by 10%, according to Samsung. Though Samsung doesn't state under what conditions – presumably, this is at iso-frequency rather than max frequency.</p>
<p>Samsung's launch of 1Tb TLC V-NAND is set to be followed by the release of a quad-level cell (QLC) model later this year.</p>
<p>"We are excited to deliver the industry’s first 9th-gen V-NAND which will bring future... SSDs&body=https://compbuddey.blogspot.com/2024/04/samsung-starts-mass-production-of-9th_28.html){kind=link}
One of the core challenges that Rapidus will face when it kicks off volume production of chips on its 2nm-class process technology in 2027 is lining up customers. With Intel, Samsung, and TSMC all slated to offer their own 2nm-class nodes by that time, Rapidus will need some kind of advantage to attract customers away from its more established rivals. To that end, the company thinks they've found their edge: fully automated packaging that will allow for shorter chip lead times than manned packaging operations.
In an interview with Nikkei, Rapidus' president, Atsuyoshi Koike, outlined the company's vision to use advanced packaging as a competitive edge for the new fab. The Hokkaido facility, which is currently under construction and is expecting to begin equipment installation this December, is already slated to both produce chips and offer advanced packaging services within the same facility, an industry first. But ultimately, Rapidus biggest plan to differentiate itself is by automating the back-end fab processes (chip packaging) to provide significantly faster turnaround times.
Rapidus is targetting back-end production in particular as, compared to front-end (lithography) production, back-end production still heavily relies on human labor. No other advanced packaging fab has fully automated the process thus far, which provides for a degree of flexibility, but slows throughput. But with automation in place to handle this aspect of chip production, Rapidus would be able to increase chip packaging efficiency and speed, which is crucial as chip assembly tasks become more complex. Rapidus is also collaborating with multiple Japanese suppliers to source materials for back-end production.
"In the past, Japanese chipmakers tried to keep their technology development exclusively in-house, which pushed up development costs and made them less competitive," Koike told Nikkei. "[Rapidus plans to] open up technology that should be standardized, bringing down costs, while handling important technology in-house."
Financially, Rapidus faces a significant challenge, needing a total of ¥5 trillion ($35 billion) by the time mass production starts in 2027. The company estimates that ¥2 trillion will be required by 2025 for prototype production. While the Japanese government has provided ¥920 billion in aid, Rapidus still needs to secure substantial funding from private investors.
Due to its lack of track record and experience of chip production as. well as limited visibility for success, Rapidus is finding it difficult to attract private financing. The company is in discussions with the government to make it easier to raise capital, including potential loan guarantees, and is hopeful that new legislation will assist in this effort.
Semiconductors
Lorem Ipsum is simply dummy text of the printing and typesetting industry. Lorem Ipsum has been the industry's.
MediaTek to Add NVIDIA G-Sync Support to Monitor Scalers, Make G-Sync Displays More Accessible
NVIDIA on Tuesday said that future monitor scalers from MediaTek will support its G-Sync technologies. NVIDIA is partnering with MediaTek to integrate its full range of G-Sync technologies into future monitors without requiring a standalone G-Sync module, which makes advanced gaming features more accessible across a broader range of displays.
Traditionally, G-Sync technology relied on a dedicated G-sync module – based on an Altera FPGA – to handle syncing display refresh rates with the GPU in order to reduce screen tearing, stutter, and input lag. As a more basic solution, in 2019 NVIDIA introduced G-Sync Compatible certification and branding, which leveraged the industry-standard VESA AdaptiveSync technology to handle variable refresh rates. In lieu of using a dedicated module, leveraging AdaptiveSync allowed for cheaper monitors, with NVIDIA's program serving as a stamp of approval that the monitor worked with NVIDIA GPUs and met NVIDIA's performance requirements. Still, G-Sync Compatible monitors still lack some features that, to date, require the dedicated G-Sync module.
Through this new partnership with MediaTek, MediaTek will bring support for all of NVIDIA's G-Sync technologies, including the latest G-Sync Pulsar, directly into their scalers. G-Sync Pulsar enhances motion clarity and reduces ghosting, providing a smoother gaming experience. In addition to variable refresh rates and Pulsar, MediaTek-based G-Sync displays will support such features as variable overdrive, 12-bit color, Ultra Low Motion Blur, low latency HDR, and Reflex Analyzer. This integration will allow more monitors to support a full range of G-Sync features without having to incorporate an expensive FPGA.
The first monitors to feature full G-Sync support without needing an NVIDIA module include the AOC Agon Pro AG276QSG2, Acer Predator XB273U F5, and ASUS ROG Swift 360Hz PG27AQNR. These monitors offer 360Hz refresh rates, 1440p resolution, and HDR support.
What remains to be seen is which specific MediaTek's scalers will support NVIDIA's G-Sync technology – or if the company is going to implement support into all of their scalers going forward. It also remains to be seen whether monitors with NVIDIA's dedicated G-Sync modules retain any advantages over displays with MediaTek's scalers.
Monitors
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