Microchip recently announced the availability of their second PCIe Gen 5 enterprise SSD controller - the Flashtec 5016. Like the 4016, this is also a 16-channel controller, but there are some key updates:
Microchip's enterprise SSD controllers provide a high level of flexibility to SSD vendors by providing them with significant horsepower and accelerators. The 5016 includes Cortex-A53 cores for SSD vendors to run custom applications relevant to SSD management. However, compared to the Gen4 controllers, there are two additional cores in the CPU cluster. The DRAM subsystem includes ECC support (both out-of-band and inline, as desired by the SSD vendor).
At FMS 2024, the company demonstrated an application of the neural network engines embedded in the Gen5 controllers. Controllers usually employ a 'read-retry' operation with altered read-out voltages for flash reads that do not complete successfully. Microchip implemented a machine learning approach to determine the read-out voltage based on the health history of the NAND block using the NN engines in the controller. This approach delivers tangible benefits for read latency and power consumption (thanks to a smaller number of errors on the first read).
The 4016 and 5016 come with a single-chip root of trust implementation for hardware security. A secure boot process with dual-signature authentication ensures that the controller firmware is not maliciously altered in the field. The company also brought out the advantages of their controller's implementation of SR-IOV, flexible data placement, and zoned namespaces along with their 'credit engine' scheme for multi-tenant cloud workloads. These aspects were also brought out in other demonstrations.
Microchip's press release included quotes from the usual NAND vendors - Solidigm, Kioxia, and Micron. On the customer front, Longsys has been using Flashtec controllers in their enterprise offerings along with YMTC NAND. It is likely that this collaboration will continue further using the new 5016 controller.
StorageDuring their opening keynote at Computex 2024, AMD announced their intention to launch a pair of new Ryzen 5000 processors for their legacy AM4 platform. The new chips, both getting the XT suffix, will be the Ryzen 9 5900XT, a 16 core Zen 3 part, while the Ryzen 7 5800XT will be an 8 core Zen 3.
The new chips are intended to underscore AMD's ongoing commitment to supporting their consumer platforms over several years. And while the specification changes are rather minor overall – the Zen 3 CPU architecture has long since been taken as far as it can reasonable go – it does give AMD a chance to refresh the platform by slinging hardware at new price points. AMD did something very similar for the Ryzen 3000 generation with the late-model Ryzen 3000 XT chips.
| AMD Ryzen 5000XT Series Processors (Zen 3) |
||||||
| AnandTech | Cores / Threads |
Base Freq |
Turbo Freq |
L2 Cache |
L3 Cache |
TDP |
| Ryzen 9 5950X | 16C / 32T | 3.4 GHz | 4.9 GHz | 8 MB | 64 MB | 105 W |
| Ryzen 9 5900XT | 16C / 32T | 3.3 GHz | 4.8 GHz | 8 MB | 64 MB | 105 W |
| Ryzen 9 5900X | 12C / 24T | 3.7 GHz | 4.8 GHz | 6 MB | 64 MB | 105 W |
| Ryzen 7 5800XT | 8C / 16T | 3.8 GHz | 4.8 GHz | 4 MB | 32 MB | 105 W |
| Ryzen 7 5800X | 8C / 16T | 3.8 GHz | 4.7 GHz | 4 MB | 32 MB | 105 W |
We've dedicated many column inches covering Zen 3 and the Ryzen 5000 series since they launched in late 2020, so there isn't anything new to add here. Zen 3 is no longer AMD's latest and greatest, but the platform as a whole is quite cheap to produce, making it a viable budget offering for new builds, or offering one last upgrade for old builds.
The Ryzen 9 5900XT is a 16 core part, and isn't to be confused with the Ryzen 9 5900X, which is a 12 core part. It ships with a peak turbo clockspeed of 4.8GHz, 100 MHz lower than the top-tier Ryzen 9 5950X. This makes it's XT designation somewhat of a misnomer compared to previous generations of XT chips, although it's clear that AMD has boxed themselves into a corner with their naming scheme, as they both need a way to designate that this is a new chip, and yet still place it below the 5950X.
Looking at the second chip, we have the Ryzen 7 5800XT. This is an 8 core part that does improve on its predecessor, offering a 4.8GHz max turbo clock that is 100MHz higher than the Ryzen 7 5800X's. Both chips otherwise share the same characteristics, including 6 MB of L2 cache and 32 MB of L3 cache, and all four of the chips – including the two new XT series and the corresponding X series chips – all come with a 105 Watt TDP.
In terms of motherboard compatibility, all of the AM4 motherboards that currently support the Ryzen 5000 series are also compatible with the Ryzen 5000XT series, although users are likely to need to perform a firmware update to ensure maximum compatibility; they are the same chips, but the microcodes are likely different.
AMD has provided some gaming performance figures comparing the Ryzen 9 5900XT to Intel's 13th Gen Core i7-13700K. It does offer very modest yet marginal gains in games by up to 4%; it's not mind-blowing, but the... CPUs
Kioxia's booth at FMS 2024 was a busy one with multiple technology demonstrations keeping visitors occupied. A walk-through of the BiCS 8 manufacturing process was the first to grab my attention. Kioxia and Western Digital announced the sampling of BiCS 8 in March 2023. We had touched briefly upon its CMOS Bonded Array (CBA) scheme in our coverage of Kioxial's 2Tb QLC NAND device and coverage of Western Digital's 128 TB QLC enterprise SSD proof-of-concept demonstration. At Kioxia's booth, we got more insights.
Traditionally, fabrication of flash chips involved placement of the associate logic circuitry (CMOS process) around the periphery of the flash array. The process then moved on to putting the CMOS under the cell array, but the wafer development process was serialized with the CMOS logic getting fabricated first followed by the cell array on top. However, this has some challenges because the cell array requires a high-temperature processing step to ensure higher reliability that can be detrimental to the health of the CMOS logic. Thanks to recent advancements in wafer bonding techniques, the new CBA process allows the CMOS wafer and cell array wafer to be processed independently in parallel and then pieced together, as shown in the models above.
The BiCS 8 3D NAND incorporates 218 layers, compared to 112 layers in BiCS 5 and 162 layers in BiCS 6. The company decided to skip over BiCS 7 (or, rather, it was probably a short-lived generation meant as an internal test vehicle). The generation retains the four-plane charge trap structure of BiCS 6. In its TLC avatar, it is available as a 1 Tbit device. The QLC version is available in two capacities - 1 Tbit and 2 Tbit.
Kioxia also noted that while the number of layers (218) doesn't compare favorably with the latest layer counts from the competition, its lateral scaling / cell shrinkage has enabled it to be competitive in terms of bit density as well as operating speeds (3200 MT/s). For reference, the latest shipping NAND from Micron - the G9 - has 276 layers with a bit density in TLC mode of 21 Gbit/mm2, and operates at up to 3600 MT/s. However, its 232L NAND operates only up to 2400 MT/s and has a bit density of 14.6 Gbit/mm2.
It must be noted that the CBA hybrid bonding process has advantages over the current processes used by other vendors - including Micron's CMOS under array (CuA) and SK hynix's 4D PUC (periphery-under-chip) developed in the late 2010s. It is expected that other NAND vendors will also move eventually to some variant of the hybrid bonding scheme used by Kioxia.
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