The AMD Ryzen 9 9950X and Ryzen 9 9900X Review: Flagship Zen 5 Soars - and Stalls
Earlier this month, AMD launched the first two desktop CPUs using their latest Zen 5 microarchitecture: the Ryzen 7 9700X and the Ryzen 5 9600X. As part of the new Ryzen 9000 family, it gave us their latest Zen 5 cores to the desktop market, as AMD actually launched Zen 5 through their mobile platform last month, the Ryzen AI 300 series (which we reviewed).
Today, AMD is launching the remaining two Ryzen 9000 SKUs first announced at Computex 2024, completing the current Ryzen 9000 product stack. Both chips hail from the premium Ryzen 9 series, which includes the flagship Ryzen 9 9950X, which has 16 Zen 5 cores and can boost as high as 5.7 GHz, while the Ryzen 9 9900X has 12 Zen 5 cores and offers boost clock speeds of up to 5.6 GHz.
Although they took slightly longer than expected to launch, as there was a delay from the initial launch date of July 31st, the full quartet of Ryzen 9000 X series processors armed with the latest Zen 5 cores are available. All of the Ryzen 9000 series processors use the same AM5 socket as the previous Ryzen 7000 (Zen 4) series, which means users can use current X670E and X670 motherboards with the new chips. Unfortunately, as we highlighted in our Ryzen 7 9700X and Ryzen 5 9600X review, the X870E/X870 motherboards, which were meant to launch alongside the Ryzen 9000 series, won't be available until sometime in September.
We've seen how the entry-level Ryzen 5 9600X and the mid-range Ryzen 7 9700X perform against the competition, but it's time to see how far and fast the flagship Ryzen 9 pairing competes. The Ryzen 9 9950X (16C/32T) and the Ryzen 9 9900X (12C/24T) both have a higher TDP (170 W/120 W respectively) than the Ryzen 7 and Ryzen 5 (65 W), but there are more cores, and Ryzen 9 is clocked faster at both base and turbo frequencies. With this in mind, it's time to see how AMD's Zen 5 flagship Ryzen 9 series for desktops performs with more firepower, with our review of the Ryzen 9 9950X and Ryzen 9 9900 processors.
CPUs
Posted by The Techinical Support
TSMC: Performance and Yields of 2nm on Track, Mass Production To Start In 2025 
In addition to revealing its roadmap and plans concerning its current leading-edge process technologies, TSMC also shared progress of its N2 node as part of its Symposiums 2024. The company's first 2nm-class fabrication node, and predominantly featuring gate-all-around transistors, according to TSMC N2 has almost achieved its target performance and yield goals, which places it on track to enter high-volume manufacturing in the second half of 2025.
TSMC states that 'N2 development is well on track and N2P is next.' In particular, gate-all-around nanosheet devices currently achieve over 90% of their expected performance, whereas yields of 256 Mb SRAM (32 MB) devices already exceeds 80%, depending on the batch. All of this for a node that is over a year away from mass production.
Meanwhile, average yield of a 256 Mb SRAM was around 70% as of March, 2024, up from around 35% in April, 2023. Device performance has also been improving with higher frequencies being achieved while keeping power consumption in check.
Chip designer interest towards TSMC's first 2nm-class gate-all-around nanosheet transistor-based technology is significant, too. The number of new tape-outs (NTOs) in the first year of N2 is over two-times higher than it was for N5. Though with that said, given TSMC's close working relationship with a handful of high-volume vendors – most notably Appe – NTOs can be a very misleading figure since the first year of a new node at TSMC is capacity constrained, and consequently the bulk of that capacity goes to TSMC's priority partners.
Meanwhile, there were considerably more N5 tapeouts in its second year (some where N5P, of course) and N2 promises to have 2.6X more NTOs in its second year. So the node indeed looks quite promising. In fact, based on TSMC's slides (which we're unfortunately not able to republish), N2 is more popular than N3 in terms of NTOs both in the first and the second years of existence.
When it comes to the second year of N2, in the second half of 2026 TSMC plans to roll out its N2P technology, which promises additional performance and power benefits. N2P is expected to improve frequency by 15% - 20%, reduce power consumption by 30% - 40%, and increase chip density by over 1.15 times compared to N3E, significant benefits to move to all-new GAA nanosheet transistors.
Finally, for those companies that need the best in performance, power, and density, TSMC is poised to offer their A16 process in 2026. That node will also bring in backside power delivery, which will add costs, but is expected to greatly improve performance efficiency and scaling.
Semiconductors
SK hynix Platinum P51 Gen5 SSD with 238L NAND Spotted at GTC 
SK hynix is set to unveil their first Gen5 consumer NVMe SSD lineup shortly, based on the products at display in their GTC 2024 booth. The Platinum P51 M.2 2280 NVMe SSD will take over flagship duties from the Platinum P41 that has been serving the market for more than a year.
Similar to the Gold P31 and the Platinum P41, the Platinum P51 also uses an in-house SSD controller. The key updates are the move to PCIe Gen5 and the use of SK hynix's 238L TLC NAND. Other details are scarce, and we have reached out for additional information.
| SK hynix Platinum P51 Gen5 NVMe SSD Specifications | ||||
| Capacity | 500 GB | 1 TB | 2 TB | |
| Controller | SK hynix In-House (Alistar) | |||
| NAND Flash | SK hynix 238L 3D TLC NAND at ?? MT/s ('4D' with CMOS circuitry under the NAND as per SK hynix marketing) | |||
| Form-Factor, Interface | M.2-2280, PCIe 5.0 x4, NVMe 2.0 | |||
| Sequential Read | 13500 MB/s | |||
| Sequential Write | 11500 MB/s | |||
| Random Read IOPS | TBD | |||
| Random Write IOPS | TBD | |||
| SLC Caching | Yes | |||
| TCG Opal Encryption | TBD | |||
| Warranty | TBD | |||
| Write Endurance | TBD | TBD | TBD | |
Only the peak sequential access numbers were available at the GTC booth, indicating that the drive's firmware is still undergoing tweaks. It is also unclear how these numbers are going to vary based on capacity. Availability and pricing are also not public yet.
This is a significant launch for the Gen5 consumer SSD market, where the number of available options are quite limited. The Phison E26 controller and Micron's B58R NAND combination is already in its second generation (with the NAND operating at 2400 MT/s in the newest avatar), but other vertically integrated vendors such as Samsung, Western Digital / Kioxia, and SK hynix (till now) are focusing more on the Gen4 market which has much higher adoption.
We will update the piece with additional information once the specifications are officially available.
Storage
TSMC's Roadmap at a Glance: N3X, N2P, A16 Coming in 2025/2026 
As announced last week by TSMC, later this year the company is set to start high-volume manufacturing on its N3P fabrication process, and this will be the company's most advanced node for a while. Next year things will get a bit more interesting as TSMC will have two process technologies that could actually compete against each other when they enter high-volume manufacturing (HVM) in the second half of 2025.
| Advertised PPA Improvements of New Process Technologies Data announced during conference calls, events, press briefings and press releases |
|||||||||
| Compiled by AnandTech |
TSMC | ||||||||
| N3 vs N5 |
N3E vs N5 |
N3P vs N3E |
N3X vs N3P |
N2 vs N3E |
N2P vs N3E |
N2P vs N2 |
A16 vs N2P |
||
| Power | -25% -30% |
-34% | -5% -10% |
-7%*** | -25% -30% |
-30% -40% |
-5% -10% |
-15% -20% |
|
| Performance | +10% +15% |
+18% | +5% | +5% Fmax @1.2V** |
+10% +15% |
+15% +20% |
+5 +10% |
+8% +10% |
|
| Density* | ? | 1.3x | 1.04x | 1.10x*** | 1.15x | 1.15x | ? | 1.07x 1.10x |
|
| HVM | Q4 2022 |
Q4 2023 |
H2 2024 |
H2 2025 |
H2 2025 |
H2 2026 |
H2 2026 |
H2 2026 |
|
*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same area.
***At the same speed.
The production nodes are N3X (3nm-class, extreme performance-focused) as well as N2 (2nm-class). TSMC says that when compared to N3P, chips made on N3X can either lower power consumption by 7% at the same frequency by lowering Vdd from 1.0V to 0.9V, increase performance by 5% at the same area, or increase transistor density by around 10% at the same frequency. Meanwhile, the key advantage of N3X compared to predecessors is its maximum voltage of 1.2V, which is important for ultra-high-performance applications, such as desktop or datacenter GPUs.
TSMC's N2 will be TSMC's first production node to use gate-all-around (GAA) nanosheet transistors and this will significantly enhance its performance, power, and are... Semiconductors
TSMC: Performance and Yields of 2nm on Track, Mass Production To Start In 2025
In addition to revealing its roadmap and plans concerning its current leading-edge process technologies, TSMC also shared progress of its N2 node as part of its Symposiums 2024. The company's first 2nm-class fabrication node, and predominantly featuring gate-all-around transistors, according to TSMC N2 has almost achieved its target performance and yield goals, which places it on track to enter high-volume manufacturing in the second half of 2025.
TSMC states that 'N2 development is well on track and N2P is next.' In particular, gate-all-around nanosheet devices currently achieve over 90% of their expected performance, whereas yields of 256 Mb SRAM (32 MB) devices already exceeds 80%, depending on the batch. All of this for a node that is over a year away from mass production.
Meanwhile, average yield of a 256 Mb SRAM was around 70% as of March, 2024, up from around 35% in April, 2023. Device performance has also been improving with higher frequencies being achieved while keeping power consumption in check.
Chip designer interest towards TSMC's first 2nm-class gate-all-around nanosheet transistor-based technology is significant, too. The number of new tape-outs (NTOs) in the first year of N2 is over two-times higher than it was for N5. Though with that said, given TSMC's close working relationship with a handful of high-volume vendors – most notably Appe – NTOs can be a very misleading figure since the first year of a new node at TSMC is capacity constrained, and consequently the bulk of that capacity goes to TSMC's priority partners.
Meanwhile, there were considerably more N5 tapeouts in its second year (some where N5P, of course) and N2 promises to have 2.6X more NTOs in its second year. So the node indeed looks quite promising. In fact, based on TSMC's slides (which we're unfortunately not able to republish), N2 is more popular than N3 in terms of NTOs both in the first and the second years of existence.
When it comes to the second year of N2, in the second half of 2026 TSMC plans to roll out its N2P technology, which promises additional performance and power benefits. N2P is expected to improve frequency by 15% - 20%, reduce power consumption by 30% - 40%, and increase chip density by over 1.15 times compared to N3E, significant benefits to move to all-new GAA nanosheet transistors.
Finally, for those companies that need the best in performance, power, and density, TSMC is poised to offer their A16 process in 2026. That node will also bring in backside power delivery, which will add costs, but is expected to greatly improve performance efficiency and scaling.
Semiconductors
SK hynix Platinum P51 Gen5 SSD with 238L NAND Spotted at GTC
SK hynix is set to unveil their first Gen5 consumer NVMe SSD lineup shortly, based on the products at display in their GTC 2024 booth. The Platinum P51 M.2 2280 NVMe SSD will take over flagship duties from the Platinum P41 that has been serving the market for more than a year.
Similar to the Gold P31 and the Platinum P41, the Platinum P51 also uses an in-house SSD controller. The key updates are the move to PCIe Gen5 and the use of SK hynix's 238L TLC NAND. Other details are scarce, and we have reached out for additional information.
| SK hynix Platinum P51 Gen5 NVMe SSD Specifications | ||||
| Capacity | 500 GB | 1 TB | 2 TB | |
| Controller | SK hynix In-House (Alistar) | |||
| NAND Flash | SK hynix 238L 3D TLC NAND at ?? MT/s ('4D' with CMOS circuitry under the NAND as per SK hynix marketing) | |||
| Form-Factor, Interface | M.2-2280, PCIe 5.0 x4, NVMe 2.0 | |||
| Sequential Read | 13500 MB/s | |||
| Sequential Write | 11500 MB/s | |||
| Random Read IOPS | TBD | |||
| Random Write IOPS | TBD | |||
| SLC Caching | Yes | |||
| TCG Opal Encryption | TBD | |||
| Warranty | TBD | |||
| Write Endurance | TBD | TBD | TBD | |
Only the peak sequential access numbers were available at the GTC booth, indicating that the drive's firmware is still undergoing tweaks. It is also unclear how these numbers are going to vary based on capacity. Availability and pricing are also not public yet.
This is a significant launch for the Gen5 consumer SSD market, where the number of available options are quite limited. The Phison E26 controller and Micron's B58R NAND combination is already in its second generation (with the NAND operating at 2400 MT/s in the newest avatar), but other vertically integrated vendors such as Samsung, Western Digital / Kioxia, and SK hynix (till now) are focusing more on the Gen4 market which has much higher adoption.
We will update the piece with additional information once the specifications are officially available.
Storage
TSMC's Roadmap at a Glance: N3X, N2P, A16 Coming in 2025/2026
As announced last week by TSMC, later this year the company is set to start high-volume manufacturing on its N3P fabrication process, and this will be the company's most advanced node for a while. Next year things will get a bit more interesting as TSMC will have two process technologies that could actually compete against each other when they enter high-volume manufacturing (HVM) in the second half of 2025.
| Advertised PPA Improvements of New Process Technologies Data announced during conference calls, events, press briefings and press releases |
|||||||||
| Compiled by AnandTech |
TSMC | ||||||||
| N3 vs N5 |
N3E vs N5 |
N3P vs N3E |
N3X vs N3P |
N2 vs N3E |
N2P vs N3E |
N2P vs N2 |
A16 vs N2P |
||
| Power | -25% -30% |
-34% | -5% -10% |
-7%*** | -25% -30% |
-30% -40% |
-5% -10% |
-15% -20% |
|
| Performance | +10% +15% |
+18% | +5% | +5% Fmax @1.2V** |
+10% +15% |
+15% +20% |
+5 +10% |
+8% +10% |
|
| Density* | ? | 1.3x | 1.04x | 1.10x*** | 1.15x | 1.15x | ? | 1.07x 1.10x |
|
| HVM | Q4 2022 |
Q4 2023 |
H2 2024 |
H2 2025 |
H2 2025 |
H2 2026 |
H2 2026 |
H2 2026 |
|
*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same area.
***At the same speed.
The production nodes are N3X (3nm-class, extreme performance-focused) as well as N2 (2nm-class). TSMC says that when compared to N3P, chips made on N3X can either lower power consumption by 7% at the same frequency by lowering Vdd from 1.0V to 0.9V, increase performance by 5% at the same area, or increase transistor density by around 10% at the same frequency. Meanwhile, the key advantage of N3X compared to predecessors is its maximum voltage of 1.2V, which is important for ultra-high-performance applications, such as desktop or datacenter GPUs.
TSMC's N2 will be TSMC's first production node to use gate-all-around (GAA) nanosheet transistors and this will significantly enhance its performance, power, and are... Semiconductors
Samsung's 128 TB-Class BM1743 Enterprise SSD Displayed at FMS 2024 
Samsung had quietly launched its BM1743 enterprise QLC SSD last month with a hefty 61.44 TB SKU. At FMS 2024, the company had the even larger 122.88 TB version of that SSD on display, alongside a few recorded benchmarking sessions. Compared to the previous generation, the BM1743 comes with a 4.1x improvement in I/O performance, improvement in data retention, and a 45% improvement in power efficiency for sequential writes.
The 128 TB-class QLC SSD boasts of sequential read speeds of 7.5 GBps and write speeds of 3 GBps. Random reads come in at 1.6 M IOPS, while 16 KB random writes clock in at 45K IOPS. Based on the quoted random write access granularity, it appears that Samsung is using a 16 KB indirection unit (IU) to optimize flash management. This is similar to the strategy adopted by Solidigm with IUs larger than 4K in their high-capacity SSDs.
A recorded benchmark session on the company's PM9D3a 8-channel Gen 5 SSD was also on display.
The SSD family is being promoted as a mainstream option for datacenters, and boasts of sequential reads up to 12 GBps and writes up to 6.8 GBps. Random reads clock in at 2 M IOPS, and random writes at 400 K IOPS.
Available in multiple form-factors up to 32 TB (M.2 tops out at 2 TB), the drive's firmware includes optional support for flexible data placement (FDP) to help address the write amplification aspect.
The PM1753 is the current enterprise SSD flagship in Samsung's lineup. With support for 16 NAND channels and capacities up to 32 TB, this U.2 / E3.S SSD has advertised sequential read and write speeds of 14.8 GBps and 11 GBps respectively. Random reads and writes for 4 KB accesses are listed at 3.4 M and 600 K IOPS.
Samsung claims a 1.7x performance improvement and a 1.7x power efficiency improvement over the previous generation (PM1743), making this TLC SSD suitable for AI servers.
The 9th Gen. V-NAND wafer was also available for viewing, though photography was prohibited. Mass production of this flash memory began in April 2024.
Storage
Fadu's FC5161 SSD Controller Breaks Cover in Western Digital's PCIe Gen5 Enterprise Drives 
When Western Digital introduced its Ultrastar DC SN861 SSDs earlier this year, the company did not disclose which controller it used for these drives, which made many observers presume that WD was using an in-house controller. But a recent teardown of the drive shows that is not the case; instead, the company is using a controller from Fadu, a South Korean company founded in 2015 that specializes on enterprise-grade turnkey SSD solutions.
The Western Digital Ultrastar DC SN861 SSD is aimed at performance-hungry hyperscale datacenters and enterprise customers which are adopting PCIe Gen5 storage devices these days. And, as uncovered in photos from a recent Storage Review article, the drive is based on Fadu's FC5161 NVMe 2.0-compliant controller. The FC5161 utilizes 16 NAND channels supporting an ONFi 5.0 2400 MT/s interface, and features a combination of enterprise-grade capabilities (OCP Cloud Spec 2.0, SR-IOV, up to 512 name spaces for ZNS support, flexible data placement, NVMe-MI 1.2, advanced security, telemetry, power loss protection) not available on other off-the-shelf controllers – or on any previous Western Digital controllers.
The Ultrastar DC SN861 SSD offers sequential read speeds up to 13.7 GB/s as well as sequential write speeds up to 7.5 GB/s. As for random performance, it boasts with an up to 3.3 million random 4K read IOPS and up to 0.8 million random 4K write IOPS. The drives are available in capacities between 1.6 TB and 7.68 TB with one or three drive writes per day (DWPD) over five years rating as well as in U.2 and E1.S form-factors.
While the two form factors of the SN861 share a similar technical design, Western Digital has tailored each version for distinct workloads: the E1.S supports FDP and performance enhancements specifically for cloud environments. By contrast, the U.2 model is geared towards high-performance enterprise tasks and emerging applications like AI.
Without any doubts, Western Digital's Ultrastar DC SN861 is a feature-rich high-performance enterprise-grade SSD. It has another distinctive feature: a 5W idle power consumption, which is rather low by the standards of enterprise-grade drives (e.g., it is 1W lower compared to the SN840). While the difference with predecessors may be just 1W, hyperscalers deploy thousands of drives and for their TCO every watt counts.
Western Digital's Ultrastar DC SN861 SSDs are now available for purchase to select customers (such as Meta) and to interested parties. Prices are unknown, but they will depend on such factors as volumes.
Sources: Fadu, Storage Review
Storage
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TSMC: Performance and Yields of 2nm on Track, Mass Production To Start In 2025
In addition to revealing its roadmap and plans concerning its current leading-edge process technologies, TSMC also shared progress of its N2 node as part of its Symposiums 2024. The company's first 2nm-class fabrication node, and predominantly featuring gate-all-around transistors, according to TSMC N2 has almost achieved its target performance and yield goals, which places it on track to enter high-volume manufacturing in the second half of 2025.
TSMC states that 'N2 development is well on track and N2P is next.' In particular, gate-all-around nanosheet devices currently achieve over 90% of their expected performance, whereas yields of 256 Mb SRAM (32 MB) devices already exceeds 80%, depending on the batch. All of this for a node that is over a year away from mass production.
Meanwhile, average yield of a 256 Mb SRAM was around 70% as of March, 2024, up from around 35% in April, 2023. Device performance has also been improving with higher frequencies being achieved while keeping power consumption in check.
Chip designer interest towards TSMC's first 2nm-class gate-all-around nanosheet transistor-based technology is significant, too. The number of new tape-outs (NTOs) in the first year of N2 is over two-times higher than it was for N5. Though with that said, given TSMC's close working relationship with a handful of high-volume vendors – most notably Appe – NTOs can be a very misleading figure since the first year of a new node at TSMC is capacity constrained, and consequently the bulk of that capacity goes to TSMC's priority partners.
Meanwhile, there were considerably more N5 tapeouts in its second year (some where N5P, of course) and N2 promises to have 2.6X more NTOs in its second year. So the node indeed looks quite promising. In fact, based on TSMC's slides (which we're unfortunately not able to republish), N2 is more popular than N3 in terms of NTOs both in the first and the second years of existence.
When it comes to the second year of N2, in the second half of 2026 TSMC plans to roll out its N2P technology, which promises additional performance and power benefits. N2P is expected to improve frequency by 15% - 20%, reduce power consumption by 30% - 40%, and increase chip density by over 1.15 times compared to N3E, significant benefits to move to all-new GAA nanosheet transistors.
Finally, for those companies that need the best in performance, power, and density, TSMC is poised to offer their A16 process in 2026. That node will also bring in backside power delivery, which will add costs, but is expected to greatly improve performance efficiency and scaling.
Semiconductors
SK hynix Platinum P51 Gen5 SSD with 238L NAND Spotted at GTC
SK hynix is set to unveil their first Gen5 consumer NVMe SSD lineup shortly, based on the products at display in their GTC 2024 booth. The Platinum P51 M.2 2280 NVMe SSD will take over flagship duties from the Platinum P41 that has been serving the market for more than a year.
Similar to the Gold P31 and the Platinum P41, the Platinum P51 also uses an in-house SSD controller. The key updates are the move to PCIe Gen5 and the use of SK hynix's 238L TLC NAND. Other details are scarce, and we have reached out for additional information.
| SK hynix Platinum P51 Gen5 NVMe SSD Specifications | ||||
| Capacity | 500 GB | 1 TB | 2 TB | |
| Controller | SK hynix In-House (Alistar) | |||
| NAND Flash | SK hynix 238L 3D TLC NAND at ?? MT/s ('4D' with CMOS circuitry under the NAND as per SK hynix marketing) | |||
| Form-Factor, Interface | M.2-2280, PCIe 5.0 x4, NVMe 2.0 | |||
| Sequential Read | 13500 MB/s | |||
| Sequential Write | 11500 MB/s | |||
| Random Read IOPS | TBD | |||
| Random Write IOPS | TBD | |||
| SLC Caching | Yes | |||
| TCG Opal Encryption | TBD | |||
| Warranty | TBD | |||
| Write Endurance | TBD | TBD | TBD | |
Only the peak sequential access numbers were available at the GTC booth, indicating that the drive's firmware is still undergoing tweaks. It is also unclear how these numbers are going to vary based on capacity. Availability and pricing are also not public yet.
This is a significant launch for the Gen5 consumer SSD market, where the number of available options are quite limited. The Phison E26 controller and Micron's B58R NAND combination is already in its second generation (with the NAND operating at 2400 MT/s in the newest avatar), but other vertically integrated vendors such as Samsung, Western Digital / Kioxia, and SK hynix (till now) are focusing more on the Gen4 market which has much higher adoption.
We will update the piece with additional information once the specifications are officially available.
Storage
TSMC's Roadmap at a Glance: N3X, N2P, A16 Coming in 2025/2026
As announced last week by TSMC, later this year the company is set to start high-volume manufacturing on its N3P fabrication process, and this will be the company's most advanced node for a while. Next year things will get a bit more interesting as TSMC will have two process technologies that could actually compete against each other when they enter high-volume manufacturing (HVM) in the second half of 2025.
| Advertised PPA Improvements of New Process Technologies Data announced during conference calls, events, press briefings and press releases |
|||||||||
| Compiled by AnandTech |
TSMC | ||||||||
| N3 vs N5 |
N3E vs N5 |
N3P vs N3E |
N3X vs N3P |
N2 vs N3E |
N2P vs N3E |
N2P vs N2 |
A16 vs N2P |
||
| Power | -25% -30% |
-34% | -5% -10% |
-7%*** | -25% -30% |
-30% -40% |
-5% -10% |
-15% -20% |
|
| Performance | +10% +15% |
+18% | +5% | +5% Fmax @1.2V** |
+10% +15% |
+15% +20% |
+5 +10% |
+8% +10% |
|
| Density* | ? | 1.3x | 1.04x | 1.10x*** | 1.15x | 1.15x | ? | 1.07x 1.10x |
|
| HVM | Q4 2022 |
Q4 2023 |
H2 2024 |
H2 2025 |
H2 2025 |
H2 2026 |
H2 2026 |
H2 2026 |
|
*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same area.
***At the same speed.
The production nodes are N3X (3nm-class, extreme performance-focused) as well as N2 (2nm-class). TSMC says that when compared to N3P, chips made on N3X can either lower power consumption by 7% at the same frequency by lowering Vdd from 1.0V to 0.9V, increase performance by 5% at the same area, or increase transistor density by around 10% at the same frequency. Meanwhile, the key advantage of N3X compared to predecessors is its maximum voltage of 1.2V, which is important for ultra-high-performance applications, such as desktop or datacenter GPUs.
TSMC's N2 will be TSMC's first production node to use gate-all-around (GAA) nanosheet transistors and this will significantly enhance its performance, power, and are... Semiconductors
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