Western Digital: We Are Sampling 32TB SMR Hard Drives <a href="https://www.anandtech.com/show/21498/western-digital-we-are-sampling-32-tb-smr-hard-drives"><img src="https://images.anandtech.com/doci/21498/western-digital-hdd-hgst-ultrastar-datacenter-server-hdd-wd-hard-drive-678_575px.jpg" alt="" /></a>In an unexpected announcement during their quarterly earnings call this week, Western Digital revealed that it has begun sampling an upcoming 32TB hard drive. The nearline HDD is aimed at hyperscalers, and relies on a combination of Westen Digital's EAMR technology, as well as shingled magnetic recording (SMR) technology to hit their highest capacity figures to date. Western Digital's 32TB HDD uses all of the company's most advanced technologies. Besides energy-assisted magnetic recording (EAMR/<a href="https://www.anandtech.com/show/18908/western-digital-estimates-hamr-hdds-to-emerge-in-15-years">ePMR 2</a> to be more precise) technology, WD is also leveraging triple-stage actuators for better positioning of heads and two-dimensional (TDMR) read heads, <a href="https://www.anandtech.com/show/16920/western-digital-reimagines-hdd-flash-integration-with-optinand">OptiNAND</a> for extra performance and reliability, distributed sector (DSEC) technology and a proprietary error correcting code (ECC) technology. And, most importantly, UltraSMR technology to provide additional capacity. "We are shipping samples of our 32TB UltraSMR/ePMR nearline hard drives to select customers," said David Goeckeler, chief executive of Western Digital, at the earnings call. "These drives feature advanced triple-stage actuators and OptiNAND technology which are designed for seamless qualification, integration and deployment in hyperscale cloud and enterprise data centers while maintaining exceptional reliability." Seagate is currently shipping its <a href="https://www.anandtech.com/show/21235/seagate-unveils-mozaic-3-hdd-platform-as-hamr-readies-for-volume-ramp">30TB Exos HDDs based on heat-assisted magnetic recording (HAMR) platform called Modaic 3+</a> to select exascalers, and the company has implied that it can build a 32TB version of the drive using SMR. Therefore, from capacity point of view, Western Digital's announcement means that the company has caught up with its rival. As with the comapny's other UltraSMR drives, the 32TB nearline drive is aimed at WD's enterprise customers, whose infrastructure can handle the additional management requirements that SMR imposes. As SMR in enterprise drives is not transparent, it's up to the host to manage many of the complexities that come with a hard drive that isn't suited for random writes. Though at least in WD's case, the upshot is that UltraSMR also offers a more significant density increase than other SMR implementations, using a larger number of SMR bands to increase HDD capacity by up to 20%. Working backwards, that 20% capacity increase also means that WD's new drive is starting from 2.56TB CMR platters. And while 2.56TB makes for a very decent areal density, this would mean that WD is still behind rival Seagate in terms of areal density overall, as Seagate has 3TB CMR platters in its latest HAMR-based Exos drives. Storage

Kioxia's High-Performance 3D QLC NAND Enables High-End High-Capacity SSDs <p align="center"><a href="https://www.anandtech.com/show/21464/kioxias-highperformance-3d-qlc-nand-enables-highend-highcapacity-ssds"><img src="https://images.anandtech.com/doci/21464/kioxia-nand-678_575px.png" alt="" /></a></p><p><p>This week, Kioxia introduced its new 3D QLC NAND devices aimed at high-performance, high-capacity drives that could redefine what we typically expect from QLC-based SSDs. The components are 1 Tb and 2 Tb 3D QLC NAND ICs with a 3600 MT/s interface speed that could enable M.2-2230 SSDs with a 4 TB capacity and decent performance.</p>

<p>Kioxia's 1 Tb (128 MB) and 2 Tb (256 TB) 3D QLC NAND devices are made on the company's BICS 8 process technology and feature 238 active layers as well as CMOS directly Bonded to Array (CBA) design, which implies that CMOS (including interface and buffers circuitry) is built on a specialized node and bonded to the memory array. Such a manufacturing process enabled Kioxia (and its manufacturing partner Western Digital) to achieve a particularly high interface speed of 3600 MT/s.</p>

<p>In addition to being one of the industry's first 2 Tb QLC NAND devices, the component features a 70% higher write power efficiency compared to Kioxia's BICS 5 3D QLC NAND devices, which is a bit vague statement as the new ICs have higher capacity and performance in general. This feature will be valuable for data centre applications, though I do not expect someone to use 3D QLC memory for write-intensive applications in general. Yet, these devices will be just what the doctor ordered for AI: read-intensive, content distribution, and backup storage.</p>

<p>It is interesting to note that Kioxia's 1 Tb 3D QLC NAND, optimized for performance, has a 30% faster sequential write performance and a 15% lower read latency than the 2 Tb 3D QLC component. These qualities (alongside a 3600 MT/s interface) promise to make Kioxia's 1 Tb 3D QLC competitive even for higher-end PCIe Gen5 x4 SSDs, which currently exclusively use 3D TLC memory.</p>

<p>The remarkable storage density of Kioxia's 2Tb 3D QLC NAND devices will allow customers to create high-capacity SSDs in compact form factors. For instance, a 16-Hi stacked package (measuring 11.5 mm × 13.5 mm × 1.5 mm) can be used to build a 4TB M.2-2230 drive or a 16TB M.2-2280 drive. Even a single 16-Hi package could be enough to build a particularly fast client SSD.</p>

<p>Kioxia is now sampling its 2 Tb 3D QLC NAND BiCS 8 memory with customers, such as Pure Storage.</p>

<p>"<em>We have a long-standing relationship with Kioxia and are delighted to incorporate their eighth-generation BiCS Flash 2Tb QLC flash memory products to enhance the performance and efficiency of our all-flash storage solutions,</em>" said Charles Giancarlo, CEO of Pure Storage. "<em>Pure's unified all-flash data storage platform is able to meet the demanding needs of artificial intelligence as well as the aggressive costs of backup storage. Backed by Kioxia technology, Pure Storage will continue to offer unmatched performance, power efficiency, and reliability, delivering exceptional value to our customers.</em>"</p>

<p>"<em>We are pleased to be shipping samples of our new 2Tb QLC with the new eighth-generation BiCS flash technology,</em>" said Hideshi Miyajima, CTO of Kioxia. "<em>With its industry-leading high bit density, high speed data transfer, and superior power efficiency, the 2Tb QLC product will offer new value for rapidly emerging AI applications and large storage applications demanding power and space savings.</em>"</p>

<p>There is no word on when the 1 Tb 3D QLC BiCS 8 memory will be sampled or released to the market.</p>
</p> SSDs

Kioxia's High-Performance 3D QLC NAND Enables High-End High-Capacity SSDs
This week, Kioxia introduced its new 3D QLC NAND devices aimed at high-performance, high-capacity drives that could redefine what we typically expect from QLC-based SSDs. The components are 1 Tb and 2 Tb 3D QLC NAND ICs with a 3600 MT/s interface speed that could enable M.2-2230 SSDs with a 4 TB capacity and decent performance.

Kioxia's 1 Tb (128 MB) and 2 Tb (256 TB) 3D QLC NAND devices are made on the company's BICS 8 process technology and feature 238 active layers as well as CMOS directly Bonded to Array (CBA) design, which implies that CMOS (including interface and buffers circuitry) is built on a specialized node and bonded to the memory array. Such a manufacturing process enabled Kioxia (and its manufacturing partner Western Digital) to achieve a particularly high interface speed of 3600 MT/s.

In addition to being one of the industry's first 2 Tb QLC NAND devices, the component features a 70% higher write power efficiency compared to Kioxia's BICS 5 3D QLC NAND devices, which is a bit vague statement as the new ICs have higher capacity and performance in general. This feature will be valuable for data centre applications, though I do not expect someone to use 3D QLC memory for write-intensive applications in general. Yet, these devices will be just what the doctor ordered for AI: read-intensive, content distribution, and backup storage.

It is interesting to note that Kioxia's 1 Tb 3D QLC NAND, optimized for performance, has a 30% faster sequential write performance and a 15% lower read latency than the 2 Tb 3D QLC component. These qualities (alongside a 3600 MT/s interface) promise to make Kioxia's 1 Tb 3D QLC competitive even for higher-end PCIe Gen5 x4 SSDs, which currently exclusively use 3D TLC memory.

The remarkable storage density of Kioxia's 2Tb 3D QLC NAND devices will allow customers to create high-capacity SSDs in compact form factors. For instance, a 16-Hi stacked package (measuring 11.5 mm × 13.5 mm × 1.5 mm) can be used to build a 4TB M.2-2230 drive or a 16TB M.2-2280 drive. Even a single 16-Hi package could be enough to build a particularly fast client SSD.

Kioxia is now sampling its 2 Tb 3D QLC NAND BiCS 8 memory with customers, such as Pure Storage.

"We have a long-standing relationship with Kioxia and are delighted to incorporate their eighth-generation BiCS Flash 2Tb QLC flash memory products to enhance the performance and efficiency of our all-flash storage solutions," said Charles Giancarlo, CEO of Pure Storage. "Pure's unified all-flash data storage platform is able to meet the demanding needs of artificial intelligence as well as the aggressive costs of backup storage. Backed by Kioxia technology, Pure Storage will continue to offer unmatched performance, power efficiency, and reliability, delivering exceptional value to our customers."

"We are pleased to be shipping samples of our new 2Tb QLC with the new eighth-generation BiCS flash technology," said Hideshi Miyajima, CTO of Kioxia. "With its industry-leading high bit density, high speed data transfer, and superior power efficiency, the 2Tb QLC product will offer new value for rapidly emerging AI applications and large storage applications demanding power and space savings."

There is no word on when the 1 Tb 3D QLC BiCS 8 memory will be sampled or released to the market.

SSDs

August 03, 2024

Kioxia Details BiCS 8 NAND at FMS 2024: 218 Layers With Superior Scaling
Kioxia's booth at FMS 2024 was a busy one with multiple technology demonstrations keeping visitors occupied. A walk-through of the BiCS 8 manufacturing process was the first to grab my attention. Kioxia and Western Digital announced the sampling of BiCS 8 in March 2023. We had touched briefly upon its CMOS Bonded Array (CBA) scheme in our coverage of Kioxial's 2Tb QLC NAND device and coverage of Western Digital's 128 TB QLC enterprise SSD proof-of-concept demonstration. At Kioxia's booth, we got more insights.

Traditionally, fabrication of flash chips involved placement of the associate logic circuitry (CMOS process) around the periphery of the flash array. The process then moved on to putting the CMOS under the cell array, but the wafer development process was serialized with the CMOS logic getting fabricated first followed by the cell array on top. However, this has some challenges because the cell array requires a high-temperature processing step to ensure higher reliability that can be detrimental to the health of the CMOS logic. Thanks to recent advancements in wafer bonding techniques, the new CBA process allows the CMOS wafer and cell array wafer to be processed independently in parallel and then pieced together, as shown in the models above.

The BiCS 8 3D NAND incorporates 218 layers, compared to 112 layers in BiCS 5 and 162 layers in BiCS 6. The company decided to skip over BiCS 7 (or, rather, it was probably a short-lived generation meant as an internal test vehicle). The generation retains the four-plane charge trap structure of BiCS 6. In its TLC avatar, it is available as a 1 Tbit device. The QLC version is available in two capacities - 1 Tbit and 2 Tbit.

Kioxia also noted that while the number of layers (218) doesn't compare favorably with the latest layer counts from the competition, its lateral scaling / cell shrinkage has enabled it to be competitive in terms of bit density as well as operating speeds (3200 MT/s). For reference, the latest shipping NAND from Micron - the G9 - has 276 layers with a bit density in TLC mode of 21 Gbit/mm², and operates at up to 3600 MT/s. However, its 232L NAND operates only up to 2400 MT/s and has a bit density of 14.6 Gbit/mm².

It must be noted that the CBA hybrid bonding process has advantages over the current processes used by other vendors - including Micron's CMOS under array (CuA) and SK hynix's 4D PUC (periphery-under-chip) developed in the late 2010s. It is expected that other NAND vendors will also move eventually to some variant of the hybrid bonding scheme used by Kioxia.

Storage

March 12, 2025

Kioxia's High-Performance 3D QLC NAND Enables High-End High-Capacity SSDs
This week, Kioxia introduced its new 3D QLC NAND devices aimed at high-performance, high-capacity drives that could redefine what we typically expect from QLC-based SSDs. The components are 1 Tb and 2 Tb 3D QLC NAND ICs with a 3600 MT/s interface speed that could enable M.2-2230 SSDs with a 4 TB capacity and decent performance.

Kioxia's 1 Tb (128 MB) and 2 Tb (256 TB) 3D QLC NAND devices are made on the company's BICS 8 process technology and feature 238 active layers as well as CMOS directly Bonded to Array (CBA) design, which implies that CMOS (including interface and buffers circuitry) is built on a specialized node and bonded to the memory array. Such a manufacturing process enabled Kioxia (and its manufacturing partner Western Digital) to achieve a particularly high interface speed of 3600 MT/s.

In addition to being one of the industry's first 2 Tb QLC NAND devices, the component features a 70% higher write power efficiency compared to Kioxia's BICS 5 3D QLC NAND devices, which is a bit vague statement as the new ICs have higher capacity and performance in general. This feature will be valuable for data centre applications, though I do not expect someone to use 3D QLC memory for write-intensive applications in general. Yet, these devices will be just what the doctor ordered for AI: read-intensive, content distribution, and backup storage.

It is interesting to note that Kioxia's 1 Tb 3D QLC NAND, optimized for performance, has a 30% faster sequential write performance and a 15% lower read latency than the 2 Tb 3D QLC component. These qualities (alongside a 3600 MT/s interface) promise to make Kioxia's 1 Tb 3D QLC competitive even for higher-end PCIe Gen5 x4 SSDs, which currently exclusively use 3D TLC memory.

The remarkable storage density of Kioxia's 2Tb 3D QLC NAND devices will allow customers to create high-capacity SSDs in compact form factors. For instance, a 16-Hi stacked package (measuring 11.5 mm × 13.5 mm × 1.5 mm) can be used to build a 4TB M.2-2230 drive or a 16TB M.2-2280 drive. Even a single 16-Hi package could be enough to build a particularly fast client SSD.

Kioxia is now sampling its 2 Tb 3D QLC NAND BiCS 8 memory with customers, such as Pure Storage.

"We have a long-standing relationship with Kioxia and are delighted to incorporate their eighth-generation BiCS Flash 2Tb QLC flash memory products to enhance the performance and efficiency of our all-flash storage solutions," said Charles Giancarlo, CEO of Pure Storage. "Pure's unified all-flash data storage platform is able to meet the demanding needs of artificial intelligence as well as the aggressive costs of backup storage. Backed by Kioxia technology, Pure Storage will continue to offer unmatched performance, power efficiency, and reliability, delivering exceptional value to our customers."

"We are pleased to be shipping samples of our new 2Tb QLC with the new eighth-generation BiCS flash technology," said Hideshi Miyajima, CTO of Kioxia. "With its industry-leading high bit density, high speed data transfer, and superior power efficiency, the 2Tb QLC product will offer new value for rapidly emerging AI applications and large storage applications demanding power and space savings."

There is no word on when the 1 Tb 3D QLC BiCS 8 memory will be sampled or released to the market.

SSDs

August 03, 2024

Kioxia Details BiCS 8 NAND at FMS 2024: 218 Layers With Superior Scaling
Kioxia's booth at FMS 2024 was a busy one with multiple technology demonstrations keeping visitors occupied. A walk-through of the BiCS 8 manufacturing process was the first to grab my attention. Kioxia and Western Digital announced the sampling of BiCS 8 in March 2023. We had touched briefly upon its CMOS Bonded Array (CBA) scheme in our coverage of Kioxial's 2Tb QLC NAND device and coverage of Western Digital's 128 TB QLC enterprise SSD proof-of-concept demonstration. At Kioxia's booth, we got more insights.

Traditionally, fabrication of flash chips involved placement of the associate logic circuitry (CMOS process) around the periphery of the flash array. The process then moved on to putting the CMOS under the cell array, but the wafer development process was serialized with the CMOS logic getting fabricated first followed by the cell array on top. However, this has some challenges because the cell array requires a high-temperature processing step to ensure higher reliability that can be detrimental to the health of the CMOS logic. Thanks to recent advancements in wafer bonding techniques, the new CBA process allows the CMOS wafer and cell array wafer to be processed independently in parallel and then pieced together, as shown in the models above.

The BiCS 8 3D NAND incorporates 218 layers, compared to 112 layers in BiCS 5 and 162 layers in BiCS 6. The company decided to skip over BiCS 7 (or, rather, it was probably a short-lived generation meant as an internal test vehicle). The generation retains the four-plane charge trap structure of BiCS 6. In its TLC avatar, it is available as a 1 Tbit device. The QLC version is available in two capacities - 1 Tbit and 2 Tbit.

Kioxia also noted that while the number of layers (218) doesn't compare favorably with the latest layer counts from the competition, its lateral scaling / cell shrinkage has enabled it to be competitive in terms of bit density as well as operating speeds (3200 MT/s). For reference, the latest shipping NAND from Micron - the G9 - has 276 layers with a bit density in TLC mode of 21 Gbit/mm², and operates at up to 3600 MT/s. However, its 232L NAND operates only up to 2400 MT/s and has a bit density of 14.6 Gbit/mm².

It must be noted that the CBA hybrid bonding process has advantages over the current processes used by other vendors - including Micron's CMOS under array (CuA) and SK hynix's 4D PUC (periphery-under-chip) developed in the late 2010s. It is expected that other NAND vendors will also move eventually to some variant of the hybrid bonding scheme used by Kioxia.

Storage

March 12, 2025

SK hynix: GDDR7 Mass Production To Start in Q4'2024 <p align="center"><a href="https://www.anandtech.com/show/21435/sk-hynix-to-start-mass-production-of-gddr7-in-q1-companys-rep"><img src="https://images.anandtech.com/doci/21435/IMG_1315-678_575px.jpg" alt="" /></a></p><p><p><em><strong>Update 06/13</strong>: SK hynix has sent a note to AnandTech clarifying that the company "plans to start mass production of GDDR7 in the fourth quarter of this year when the relevant market opens up." This article has been updated accordingly.</em></p>

<p>Being a major JEDEC memory standard, GDDR7 is slated to be produced by all three of the Big Three memory manufacturers. But it seems that not all three vendors will be kicking off mass production at the same time.</p>

<p>SK hynix was at this year's Computex trade show, showing off their full lineup of memory technologies – including, of course, GDDR7. SK hynix is the last of the major memory vendor's we've seen promoting their memory, and fittingly, they seem to be the last in terms of their mass production schedule. According to company representatives, the firm will kick off mass production of their GDDR7 chips in the last quarter of 2024.</p>

<p style="text-align: center;"><a href="https://www.anandtech.com/show/21435/sk-hynix-to-start-mass-production-of-gddr7-in-q1-companys-rep"><img alt="" src="https://images.anandtech.com/doci/21435/skhynix_gddr7_chips_575px.jpg" /></a></p>

<p>Comparatively, the company's cross-town rival, Samsung, is already sampling memory with the goal of getting it out the door in 2024. And Micron has been rather gung ho about not only starting mass production this year, but starting it early enough that at least some of their customers will be able to ship finished products this year.</p>

<p>That said, it bears mentioning that with industry-standard memory technologies, mass production at one vendor does not indicate that another is late; it is just indicating that someone was first to validate with a partner and that partner plans to ship its product in 2024. And while mass production remains another 4+ months out, SK hynix does have sample chips for its partners to test right now, and the chips have been demonstrated at Computex.</p>

<p style="text-align: center;"><a href="https://www.anandtech.com/show/21435/sk-hynix-to-start-mass-production-of-gddr7-in-q1-companys-rep"><img alt="" src="https://images.anandtech.com/doci/21435/skhynix_gddr7_specs_575px.jpg" /></a></p>

<p>As far as SK hynix's floor booth at Computex 2024 is concerned, the company had GDDR7 chips on display along with a table essentially summarizing the company's roadmap. For now, SK hynix is planning on both 16Gbit and 24Gbit chips, with data transfer rates of up to 40 GT/s. Though when SK hynix intends to launch their higher-end configurations remains to be seen. Both of the company's rivals are starting out with 16Gbit chips running at 32 GT/sec, so being the first to get a faster/larger chip out would be a feather in SK hynix's cap.</p>
</p> GPUs

SK hynix: GDDR7 Mass Production To Start in Q4'2024
Update 06/13: SK hynix has sent a note to AnandTech clarifying that the company "plans to start mass production of GDDR7 in the fourth quarter of this year when the relevant market opens up." This article has been updated accordingly.

Being a major JEDEC memory standard, GDDR7 is slated to be produced by all three of the Big Three memory manufacturers. But it seems that not all three vendors will be kicking off mass production at the same time.

SK hynix was at this year's Computex trade show, showing off their full lineup of memory technologies – including, of course, GDDR7. SK hynix is the last of the major memory vendor's we've seen promoting their memory, and fittingly, they seem to be the last in terms of their mass production schedule. According to company representatives, the firm will kick off mass production of their GDDR7 chips in the last quarter of 2024.

Comparatively, the company's cross-town rival, Samsung, is already sampling memory with the goal of getting it out the door in 2024. And Micron has been rather gung ho about not only starting mass production this year, but starting it early enough that at least some of their customers will be able to ship finished products this year.

That said, it bears mentioning that with industry-standard memory technologies, mass production at one vendor does not indicate that another is late; it is just indicating that someone was first to validate with a partner and that partner plans to ship its product in 2024. And while mass production remains another 4+ months out, SK hynix does have sample chips for its partners to test right now, and the chips have been demonstrated at Computex.

As far as SK hynix's floor booth at Computex 2024 is concerned, the company had GDDR7 chips on display along with a table essentially summarizing the company's roadmap. For now, SK hynix is planning on both 16Gbit and 24Gbit chips, with data transfer rates of up to 40 GT/s. Though when SK hynix intends to launch their higher-end configurations remains to be seen. Both of the company's rivals are starting out with 16Gbit chips running at 32 GT/sec, so being the first to get a faster/larger chip out would be a feather in SK hynix's cap.

GPUs

June 27, 2024

TSMC: Performance and Yields of 2nm on Track, Mass Production To Start In 2025 <p align="center"><a href="https://www.anandtech.com/show/21413/tsmc-performance-and-yields-of-2nm-on-track-mass-production-to-start-in-2025"><img src="https://images.anandtech.com/doci/21413/tsmc-678-nanosheet-gaa-transistor_575px.jpg" alt="" /></a></p><p><p>In addition to revealing its roadmap and plans concerning its current leading-edge process technologies, TSMC also shared progress of its <a href="https://www.anandtech.com/show/21370/tsmc-2nm-update-n2-in-2025-n2p-loses-bspdn-nanoflex-optimizations">N2</a> node as part of its <a href="https://www.anandtech.com/tag/tsmc-symposium-2024">Symposiums 2024.</a> The company's first 2nm-class fabrication node, and predominantly featuring gate-all-around transistors, according to TSMC N2 has almost achieved its target performance and yield goals, which places it on track to enter high-volume manufacturing in the second half of 2025.</p>

<p>TSMC states that 'N2 development is well on track and N2P is next.' In particular, gate-all-around nanosheet devices currently achieve over 90% of their expected performance, whereas yields of 256 Mb SRAM (32 MB) devices already exceeds 80%, depending on the batch. All of this for a node that is over a year away from mass production.</p>

<p>Meanwhile, average yield of a 256 Mb SRAM was around 70% as of March, 2024, up from around 35% in April, 2023. Device performance has also been improving with higher frequencies being achieved while keeping power consumption in check.</p>

<p>Chip designer interest towards TSMC's first 2nm-class gate-all-around nanosheet transistor-based technology is significant, too. The number of new tape-outs (NTOs) in the first year of N2 is over two-times higher than it was for N5. Though with that said, given TSMC's close working relationship with a handful of high-volume vendors – most notably Appe – NTOs can be a very misleading figure since the first year of a new node at TSMC is capacity constrained, and consequently the bulk of that capacity goes to TSMC's priority partners.</p>

<p>Meanwhile, there were considerably more N5 tapeouts in its second year (some where N5P, of course) and N2 promises to have 2.6X more NTOs in its second year. So the node indeed looks quite promising. In fact, based on TSMC's slides (which we're unfortunately not able to republish), N2 is more popular than N3 in terms of NTOs both in the first and the second years of existence.</p>

<p>When it comes to the second year of N2, in the second half of 2026 TSMC plans to roll out its N2P technology, which promises additional performance and power benefits. N2P is expected to improve frequency by 15% - 20%, reduce power consumption by 30% - 40%, and increase chip density by over 1.15 times compared to N3E, significant benefits to move to all-new GAA nanosheet transistors.</p>

<p>Finally, for those companies that need the best in performance, power, and density, TSMC is poised to offer their <a href="https://www.anandtech.com/show/21408/tsmc-roadmap-at-a-glance-n3x-n2p-a16-2025-2026">A16 process in 2026</a>. That node <a href="https://www.anandtech.com/show/21369/tsmcs-16nm-technology-announced-for-late-2026-a16-with-super-power-rail-bspdn">will also bring in backside power delivery</a>, which will add costs, but is expected to greatly improve performance efficiency and scaling.</p>
</p> Semiconductors

TSMC: Performance and Yields of 2nm on Track, Mass Production To Start In 2025
In addition to revealing its roadmap and plans concerning its current leading-edge process technologies, TSMC also shared progress of its N2 node as part of its Symposiums 2024. The company's first 2nm-class fabrication node, and predominantly featuring gate-all-around transistors, according to TSMC N2 has almost achieved its target performance and yield goals, which places it on track to enter high-volume manufacturing in the second half of 2025.

TSMC states that 'N2 development is well on track and N2P is next.' In particular, gate-all-around nanosheet devices currently achieve over 90% of their expected performance, whereas yields of 256 Mb SRAM (32 MB) devices already exceeds 80%, depending on the batch. All of this for a node that is over a year away from mass production.

Meanwhile, average yield of a 256 Mb SRAM was around 70% as of March, 2024, up from around 35% in April, 2023. Device performance has also been improving with higher frequencies being achieved while keeping power consumption in check.

Chip designer interest towards TSMC's first 2nm-class gate-all-around nanosheet transistor-based technology is significant, too. The number of new tape-outs (NTOs) in the first year of N2 is over two-times higher than it was for N5. Though with that said, given TSMC's close working relationship with a handful of high-volume vendors – most notably Appe – NTOs can be a very misleading figure since the first year of a new node at TSMC is capacity constrained, and consequently the bulk of that capacity goes to TSMC's priority partners.

Meanwhile, there were considerably more N5 tapeouts in its second year (some where N5P, of course) and N2 promises to have 2.6X more NTOs in its second year. So the node indeed looks quite promising. In fact, based on TSMC's slides (which we're unfortunately not able to republish), N2 is more popular than N3 in terms of NTOs both in the first and the second years of existence.

When it comes to the second year of N2, in the second half of 2026 TSMC plans to roll out its N2P technology, which promises additional performance and power benefits. N2P is expected to improve frequency by 15% - 20%, reduce power consumption by 30% - 40%, and increase chip density by over 1.15 times compared to N3E, significant benefits to move to all-new GAA nanosheet transistors.

Finally, for those companies that need the best in performance, power, and density, TSMC is poised to offer their A16 process in 2026. That node will also bring in backside power delivery, which will add costs, but is expected to greatly improve performance efficiency and scaling.

Semiconductors

June 13, 2024

Kioxia's High-Performance 3D QLC NAND Enables High-End High-Capacity SSDs
This week, Kioxia introduced its new 3D QLC NAND devices aimed at high-performance, high-capacity drives that could redefine what we typically expect from QLC-based SSDs. The components are 1 Tb and 2 Tb 3D QLC NAND ICs with a 3600 MT/s interface speed that could enable M.2-2230 SSDs with a 4 TB capacity and decent performance.

Kioxia's 1 Tb (128 MB) and 2 Tb (256 TB) 3D QLC NAND devices are made on the company's BICS 8 process technology and feature 238 active layers as well as CMOS directly Bonded to Array (CBA) design, which implies that CMOS (including interface and buffers circuitry) is built on a specialized node and bonded to the memory array. Such a manufacturing process enabled Kioxia (and its manufacturing partner Western Digital) to achieve a particularly high interface speed of 3600 MT/s.

In addition to being one of the industry's first 2 Tb QLC NAND devices, the component features a 70% higher write power efficiency compared to Kioxia's BICS 5 3D QLC NAND devices, which is a bit vague statement as the new ICs have higher capacity and performance in general. This feature will be valuable for data centre applications, though I do not expect someone to use 3D QLC memory for write-intensive applications in general. Yet, these devices will be just what the doctor ordered for AI: read-intensive, content distribution, and backup storage.

It is interesting to note that Kioxia's 1 Tb 3D QLC NAND, optimized for performance, has a 30% faster sequential write performance and a 15% lower read latency than the 2 Tb 3D QLC component. These qualities (alongside a 3600 MT/s interface) promise to make Kioxia's 1 Tb 3D QLC competitive even for higher-end PCIe Gen5 x4 SSDs, which currently exclusively use 3D TLC memory.

The remarkable storage density of Kioxia's 2Tb 3D QLC NAND devices will allow customers to create high-capacity SSDs in compact form factors. For instance, a 16-Hi stacked package (measuring 11.5 mm × 13.5 mm × 1.5 mm) can be used to build a 4TB M.2-2230 drive or a 16TB M.2-2280 drive. Even a single 16-Hi package could be enough to build a particularly fast client SSD.

Kioxia is now sampling its 2 Tb 3D QLC NAND BiCS 8 memory with customers, such as Pure Storage.

"We have a long-standing relationship with Kioxia and are delighted to incorporate their eighth-generation BiCS Flash 2Tb QLC flash memory products to enhance the performance and efficiency of our all-flash storage solutions," said Charles Giancarlo, CEO of Pure Storage. "Pure's unified all-flash data storage platform is able to meet the demanding needs of artificial intelligence as well as the aggressive costs of backup storage. Backed by Kioxia technology, Pure Storage will continue to offer unmatched performance, power efficiency, and reliability, delivering exceptional value to our customers."

"We are pleased to be shipping samples of our new 2Tb QLC with the new eighth-generation BiCS flash technology," said Hideshi Miyajima, CTO of Kioxia. "With its industry-leading high bit density, high speed data transfer, and superior power efficiency, the 2Tb QLC product will offer new value for rapidly emerging AI applications and large storage applications demanding power and space savings."

There is no word on when the 1 Tb 3D QLC BiCS 8 memory will be sampled or released to the market.

SSDs

July 28, 2024

Realtek Outlines SSD Controller Roadmap: High-End PCIe 5.0 x4 Platform in the Works <p align="center"><a href="https://www.anandtech.com/show/21441/realtek-unwraps-ssd-controller-roadmap-highend-pcie-50-x4-platform-in-the-works"><img src="https://images.anandtech.com/doci/21441/realtek-ssd-678_575px.jpg" alt="" /></a></p><p><p>While Realtek is best known in the enthusiast space for for its peripheral controllers such as audio codecs and network controllers, the company also has a small-but-respectable SSD controller business that tends to fly under the radar due to its focus on entry-level and mainstream drives. But Realtek's stature in the SSD space is on the rise, as the company is not only planning new PCIe Gen5 SSD controllers, but also their first high-end, DRAM-equipped SSD controller.</p>

<p>For this year's Computex trade show, Realtek laid out a new SSD controller roadmap that calls for the company to release a trio of new SSD controllers over the next couple of years. First up is a new four-channel entry-level PCIe 4.0 controller, the RTS5776DL, which will be joined a bit later by a PCIe 5.0 variant, the RTS5781DL. But most interesting on Realtek's new roadmap is the final chip being planned: the eight-channel, DRAM-equipped RTS5782, which would be the company's first high-end SSD controller, capable of hitting sequential read rates as high as 14GB/second.</p>

<table align="center" border="1" cellpadding="1" cellspacing="1" width="95%">
<tbody>
<tr class="tgrey">
<td align="center" colspan="10">Realtek NVMe SSD Controller Comparison</td>
</tr>
<tr class="tlblue">
<td style="width: 130px;"> </td>
<td style="width: 90px;">RTS5782</td>
<td style="width: 90px;">RTS5781DL</td>
<td style="width: 90px;">RTS5776DL</td>
<td style="width: 90px;">RTS5772DL</td>
<td style="width: 90px;">RTS5766DL</td>
</tr>
<tr>
<td class="tlgrey">Market Segment</td>
<td style="text-align: center;">High-End</td>
<td colspan="3" style="text-align: center;">Mainstream</td>
<td rowspan="1" style="text-align: center;">Entry-Level</td>
</tr>
<tr>
<td class="tlgrey">Error Correction</td>
<td colspan="3" style="text-align: center;">4K LDPC</td>
<td colspan="2" style="text-align: center;">2K LDPC</td>
</tr>
<tr>
<td class="tlgrey" rowspan="1">DRAM</td>
<td rowspan="1" style="text-align: center;">DDR4, LPDDR4(X)</td>
<td rowspan="1" style="text-align: center;">No</td>
<td rowspan="1" style="text-align: center;">No</td>
<td rowspan="1" style="text-align: center;">No</td>
<td rowspan="1" style="text-align: center;">No</td>
</tr>
<tr>
<td class="tlgrey">Host Interface</td>
<td style="text-align: center;">PCIe 5.0 x4</td>
<td style="text-align: center;">PCIe 5.0 x4</td>
<td style="text-align: center;">PCIe 4.0 x4</td>
<td rowspan="1" style="text-align: center;">PCIe 4.0 x4</td>
<td rowspan="1" style="text-align: center;">PCIe 3.0 x4</td>
</tr>
<tr>
<td class="tlgrey">NVMe Version</td>
<td style="text-align: center;">NVMe 2.0</td>
<td style="text-align: center;">NVMe 2.0</td>
<td style="text-align: center;">NVMe 2.0</td>
<td style="text-align: center;">NVMe 1.4</td>
<td style="text-align: center;">NVMe 1.4</td>
</tr>
<tr>
<td class="tlgrey" rowspan="1">NAND Channels, Interface Speed</td>
<td rowspan="1" style="text-align: center;">8 ch,<br />
3600 MT/s</td>
<td rowspan="1" style="text-align: center;">4 ch,<br />
3600 MT/s</td>
<td rowspan="1" style="text-align: center;">4 ch,<br />
3600 MT/s</td>
<td rowspan="1" style="text-align: center;">8 ch,<br />
1600 MT/s</td>
<td rowspan="1" style="text-align: center;">4 ch,<br />
1200 MT/s</td>
</tr>
<tr>
<td class="tlgrey">Sequential Read</td>
<td style="text-align: center;">14 GB/s</td>
<td style="text-align: center;">10 GB/s</td>
<td style="text-align: center;">7.4 GB/s</td>
<td style="text-align: center;">6 GB/s</td>
<td style="text-align: center;">3.2 GB/s</td>
</tr>
<tr>
<td class="tlgrey">Sequential Write</td>
<td style="text-align: center;">12 GB/s</td>
<td style="text-align: center;">10 GB/s</td>
<td style="text-align: center;">7.4 GB/s</td>
<td style="text-align: center;">6 GB/s</td>
<td style="text-align: center;">2.2 GB/s</td>
</tr>
<tr>
<td class="tlgrey">4KB Random Read IOPS</td>
<td style="text-align: center;">2500k</td>
<td style="text-align: center;">1400k</td>
<td style="text-align: center;">1200k</td>
<td style="text-align: center;">-</td>
<td style="text-align: center;">-</td>
</tr>
<tr>
<td class="tlgrey">4KB Random Write IOPS</td>
<td style="text-align: center;">2500k</td>
<td style="text-align: center;">1400k</td>
<td style="text-align: center;">1200k</td>
<td style="text-align: center;">-</td>
<td style="text-align: center;">-</td>
</tr>
</tbody>
</table>

<p>Diving a bit deeper into Realtek's roadmap, the RTS5776DL is traditional DRAM-less PCIe Gen4 x4 controller with four NAND chann... SSDs

Realtek Outlines SSD Controller Roadmap: High-End PCIe 5.0 x4 Platform in the Works
While Realtek is best known in the enthusiast space for for its peripheral controllers such as audio codecs and network controllers, the company also has a small-but-respectable SSD controller business that tends to fly under the radar due to its focus on entry-level and mainstream drives. But Realtek's stature in the SSD space is on the rise, as the company is not only planning new PCIe Gen5 SSD controllers, but also their first high-end, DRAM-equipped SSD controller.

For this year's Computex trade show, Realtek laid out a new SSD controller roadmap that calls for the company to release a trio of new SSD controllers over the next couple of years. First up is a new four-channel entry-level PCIe 4.0 controller, the RTS5776DL, which will be joined a bit later by a PCIe 5.0 variant, the RTS5781DL. But most interesting on Realtek's new roadmap is the final chip being planned: the eight-channel, DRAM-equipped RTS5782, which would be the company's first high-end SSD controller, capable of hitting sequential read rates as high as 14GB/second.

Realtek NVMe SSD Controller Comparison

RTS5782 RTS5781DL RTS5776DL RTS5772DL RTS5766DL

Market Segment High-End Mainstream Entry-Level

Error Correction 4K LDPC 2K LDPC

DRAM DDR4, LPDDR4(X) No No No No

Host Interface PCIe 5.0 x4 PCIe 5.0 x4 PCIe 4.0 x4 PCIe 4.0 x4 PCIe 3.0 x4

NVMe Version NVMe 2.0 NVMe 2.0 NVMe 2.0 NVMe 1.4 NVMe 1.4

NAND Channels, Interface Speed 8 ch,
3600 MT/s 4 ch,
3600 MT/s 4 ch,
3600 MT/s 8 ch,
1600 MT/s 4 ch,
1200 MT/s

Sequential Read 14 GB/s 10 GB/s 7.4 GB/s 6 GB/s 3.2 GB/s

Sequential Write 12 GB/s 10 GB/s 7.4 GB/s 6 GB/s 2.2 GB/s

4KB Random Read IOPS 2500k 1400k 1200k - -

4KB Random Write IOPS 2500k 1400k 1200k - -

Diving a bit deeper into Realtek's roadmap, the RTS5776DL is traditional DRAM-less PCIe Gen4 x4 controller with four NAND chann... SSDs

June 25, 2024

Kioxia's High-Performance 3D QLC NAND Enables High-End High-Capacity SSDs
This week, Kioxia introduced its new 3D QLC NAND devices aimed at high-performance, high-capacity drives that could redefine what we typically expect from QLC-based SSDs. The components are 1 Tb and 2 Tb 3D QLC NAND ICs with a 3600 MT/s interface speed that could enable M.2-2230 SSDs with a 4 TB capacity and decent performance.

Kioxia's 1 Tb (128 MB) and 2 Tb (256 TB) 3D QLC NAND devices are made on the company's BICS 8 process technology and feature 238 active layers as well as CMOS directly Bonded to Array (CBA) design, which implies that CMOS (including interface and buffers circuitry) is built on a specialized node and bonded to the memory array. Such a manufacturing process enabled Kioxia (and its manufacturing partner Western Digital) to achieve a particularly high interface speed of 3600 MT/s.

In addition to being one of the industry's first 2 Tb QLC NAND devices, the component features a 70% higher write power efficiency compared to Kioxia's BICS 5 3D QLC NAND devices, which is a bit vague statement as the new ICs have higher capacity and performance in general. This feature will be valuable for data centre applications, though I do not expect someone to use 3D QLC memory for write-intensive applications in general. Yet, these devices will be just what the doctor ordered for AI: read-intensive, content distribution, and backup storage.

It is interesting to note that Kioxia's 1 Tb 3D QLC NAND, optimized for performance, has a 30% faster sequential write performance and a 15% lower read latency than the 2 Tb 3D QLC component. These qualities (alongside a 3600 MT/s interface) promise to make Kioxia's 1 Tb 3D QLC competitive even for higher-end PCIe Gen5 x4 SSDs, which currently exclusively use 3D TLC memory.

The remarkable storage density of Kioxia's 2Tb 3D QLC NAND devices will allow customers to create high-capacity SSDs in compact form factors. For instance, a 16-Hi stacked package (measuring 11.5 mm × 13.5 mm × 1.5 mm) can be used to build a 4TB M.2-2230 drive or a 16TB M.2-2280 drive. Even a single 16-Hi package could be enough to build a particularly fast client SSD.

Kioxia is now sampling its 2 Tb 3D QLC NAND BiCS 8 memory with customers, such as Pure Storage.

"We have a long-standing relationship with Kioxia and are delighted to incorporate their eighth-generation BiCS Flash 2Tb QLC flash memory products to enhance the performance and efficiency of our all-flash storage solutions," said Charles Giancarlo, CEO of Pure Storage. "Pure's unified all-flash data storage platform is able to meet the demanding needs of artificial intelligence as well as the aggressive costs of backup storage. Backed by Kioxia technology, Pure Storage will continue to offer unmatched performance, power efficiency, and reliability, delivering exceptional value to our customers."

"We are pleased to be shipping samples of our new 2Tb QLC with the new eighth-generation BiCS flash technology," said Hideshi Miyajima, CTO of Kioxia. "With its industry-leading high bit density, high speed data transfer, and superior power efficiency, the 2Tb QLC product will offer new value for rapidly emerging AI applications and large storage applications demanding power and space savings."

There is no word on when the 1 Tb 3D QLC BiCS 8 memory will be sampled or released to the market.

SSDs

August 03, 2024

Kioxia Details BiCS 8 NAND at FMS 2024: 218 Layers With Superior Scaling
Kioxia's booth at FMS 2024 was a busy one with multiple technology demonstrations keeping visitors occupied. A walk-through of the BiCS 8 manufacturing process was the first to grab my attention. Kioxia and Western Digital announced the sampling of BiCS 8 in March 2023. We had touched briefly upon its CMOS Bonded Array (CBA) scheme in our coverage of Kioxial's 2Tb QLC NAND device and coverage of Western Digital's 128 TB QLC enterprise SSD proof-of-concept demonstration. At Kioxia's booth, we got more insights.

Traditionally, fabrication of flash chips involved placement of the associate logic circuitry (CMOS process) around the periphery of the flash array. The process then moved on to putting the CMOS under the cell array, but the wafer development process was serialized with the CMOS logic getting fabricated first followed by the cell array on top. However, this has some challenges because the cell array requires a high-temperature processing step to ensure higher reliability that can be detrimental to the health of the CMOS logic. Thanks to recent advancements in wafer bonding techniques, the new CBA process allows the CMOS wafer and cell array wafer to be processed independently in parallel and then pieced together, as shown in the models above.

The BiCS 8 3D NAND incorporates 218 layers, compared to 112 layers in BiCS 5 and 162 layers in BiCS 6. The company decided to skip over BiCS 7 (or, rather, it was probably a short-lived generation meant as an internal test vehicle). The generation retains the four-plane charge trap structure of BiCS 6. In its TLC avatar, it is available as a 1 Tbit device. The QLC version is available in two capacities - 1 Tbit and 2 Tbit.

Kioxia also noted that while the number of layers (218) doesn't compare favorably with the latest layer counts from the competition, its lateral scaling / cell shrinkage has enabled it to be competitive in terms of bit density as well as operating speeds (3200 MT/s). For reference, the latest shipping NAND from Micron - the G9 - has 276 layers with a bit density in TLC mode of 21 Gbit/mm², and operates at up to 3600 MT/s. However, its 232L NAND operates only up to 2400 MT/s and has a bit density of 14.6 Gbit/mm².

It must be noted that the CBA hybrid bonding process has advantages over the current processes used by other vendors - including Micron's CMOS under array (CuA) and SK hynix's 4D PUC (periphery-under-chip) developed in the late 2010s. It is expected that other NAND vendors will also move eventually to some variant of the hybrid bonding scheme used by Kioxia.

Storage

March 12, 2025

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