Intel to Launch "Lunar Lake" Core Ultra Chips on September 3rd
Intel’s next-generation Core Ultra laptop chips finally have a launch date: September 3rd.
Codenamed Lunar Lake, Intel has been touting the chips for nearly a year now. Most recently, Intel offered the press a deep dive briefing on the chips and their underlying architectures at Computex back in June, along with a public preview during the company’s Computex keynote. At the time Intel was preparing for Q3’2024 launch, and that window has finally been narrowed down to a single date – September 3rd – when Intel will be hosting their Lunar Lake launch event ahead of IFA.
Intel’s second stab at a high volume chiplet-based processor for laptop users, Lunar Lake is aimed particularly at ultrabooks and other low-power mobile devices, with Intel looking to wrestle back the title of the most efficient PC laptop SoC. Lunar Lake is significant in this respect as Intel has never previously developed a whole chip architecture specifically for low power mobile devices before – it’s always been a scaled-down version of a wider-range architecture, such as the current Meteor Lake (Core Ultra 100 series). Consequently, Intel has been touting that they’ve made some serious efficiency advancements with their highly targeted chip, which they believe will vault them over the competition.
All told, Lunar Lake is slated to bring a significant series of updates to Intel’s chip architectures and chip design strategies. Of particular interest is the switch to on-package LPDDR5X memory, which is a first for a high-volume Core chip. As well, Lunar Lake incorporates updated versions of virtually every one of Intel’s architecture, from the CPU P and E cores – Lion Cove and Skymont respectively – to the Xe2 GPU and 4th generation NPU (aptly named NPU 4). And, in a scandalous twist, both of the chiplets/tiles on the CPU are being made by TSMC. Intel isn’t providing any of the active silicon for the chip – though they are providing the Foveros packaging needed to put it together.
| Intel CPU Architecture Generations | |||||
| Alder/Raptor Lake | Meteor Lake |
Lunar Lake |
Arrow Lake |
Panther Lake |
|
| P-Core Architecture | Golden Cove/ Raptor Cove |
Redwood Cove | Lion Cove | Lion Cove | Cougar Cove? |
| E-Core Architecture | Gracemont | Crestmont | Skymont | Crestmont? | Darkmont? |
| GPU Architecture | Xe-LP | Xe-LPG | Xe2 | Xe2? | ? |
| NPU Architecture | N/A | NPU 3720 | NPU 4 | ? | ? |
| Active Tiles | 1 (Monolithic) | 4 | 2 | 4? | ? |
| Manufacturing Processes | Intel 7 | Intel 4 + TSMC N6 + TSMC N5 | TSMC N3B + TSMC N6 | Intel 20A + More | Intel 18A |
| Segment | Mobile + Desktop | Mobile | LP Mobile | HP Mobile + Desktop | Mobile? |
| Release Date (OEM) | Q4'2021 | Q4'2023 | Q3'2024 | Q4'2024 | 2025 |
Suffice it to say, no matter what happens, Lunar Lake and the Core Ultra 200 series should prove to be an interesting launch.
It’s worth noting, however, that while Intel’s announcement of their livestreamed event is being labeled a “launch event&rd... CPUs
Posted by The Techinical Support
U.S. Signs $1.5B in CHIPS Act Agreements With Amkor and SKhynix for Chip Packaging Plants 
Under the CHIPS & Science Act, the U.S. government provided tens of billions of dollars in grants and loans to the world's leading maker of chips, such as Intel, Samsung, and TSMC, which will significantly expand the country's semiconductor production industry in the coming years. However, most chips are typically tested, assembled, and packaged in Asia, which has left the American supply chain incomplete. Addressing this last gap in the government's domestic chip production plans, these past couple of weeks the U.S. government signed memorandums of understanding worth about $1.5 billion with Amkor and SK hynix to support their efforts to build chip packaging facilities in the U.S.
Amkor to Build Advanced Packaging Facility with Apple in Mind
Amkor plans to build a $2 billion advanced packaging facility near Peoria, Arizona, to test and assemble chips produced by TSMC at its Fab 21 near Phoenix, Arizona. The company signed a MOU that offers $400 million in direct funding and access to $200 million in loans under the CHIPS & Science Act. In addition, the company plans to take advantage of a 25% investment tax credit on eligible capital expenditures.
Set to be strategically positioned near TSMC's upcoming Fab 21 complex in Arizona, Amkor's Peoria facility will occupy 55 acres and, when fully completed, will feature over 500,000 square feet (46,451 square meters) of cleanroom space, more than twice the size of Amkor's advanced packaging site in Vietnam. Although the company has not disclosed the exact capacity or the specific technologies the facility will support, it is expected to cater to a wide range of industries, including automotive, high-performance computing, and mobile technologies. This suggests the new plant will offer diverse packaging solutions, including traditional, 2.5D, and 3D technologies.
Amkor has collaborated extensively with Apple on the vision and initial setup of the Peoria facility, as Apple is slated to be the facility's first and largest customer, marking a significant commitment from the tech giant. This partnership highlights the importance of the new facility in reinforcing the U.S. semiconductor supply chain and positioning Amkor as a key partner for companies relying on TSMC's manufacturing capabilities. The project is expected to generate around 2,000 jobs and is scheduled to begin operations in 2027.
SK hynix to Build HBM4 in the U.S.
This week SK hynix also signed a preliminary agreement with the U.S. government to receive up to $450 million in direct funding and $500 million in loans to build an advanced memory packaging facility in West Lafayette, Indiana.
The proposed facility is scheduled to begin operations in 2028, which means that it will assemble HBM4 or HBM4E memory. Meanwhile, DRAM devices for high bandwidth memory (HBM) stacks will still be produced in South Korea. Nonetheless, packing finished HBM4/HBM4E in the U.S. and possibly integrating these memory modules with high-end processors is a big deal.
In addition to building its packaging plant, SK hynix plans to collaborate with Purdue University and other local research institutions to advance semiconductor technology and packaging innovations. This partnership is intended to bolster research and development in the region, positioning the facility as a hub for AI technology and skilled employment.
Semiconductors
U.S. Signs $1.5B in CHIPS Act Agreements With Amkor and SKhynix for Chip Packaging Plants
Under the CHIPS & Science Act, the U.S. government provided tens of billions of dollars in grants and loans to the world's leading maker of chips, such as Intel, Samsung, and TSMC, which will significantly expand the country's semiconductor production industry in the coming years. However, most chips are typically tested, assembled, and packaged in Asia, which has left the American supply chain incomplete. Addressing this last gap in the government's domestic chip production plans, these past couple of weeks the U.S. government signed memorandums of understanding worth about $1.5 billion with Amkor and SK hynix to support their efforts to build chip packaging facilities in the U.S.
Amkor to Build Advanced Packaging Facility with Apple in Mind
Amkor plans to build a $2 billion advanced packaging facility near Peoria, Arizona, to test and assemble chips produced by TSMC at its Fab 21 near Phoenix, Arizona. The company signed a MOU that offers $400 million in direct funding and access to $200 million in loans under the CHIPS & Science Act. In addition, the company plans to take advantage of a 25% investment tax credit on eligible capital expenditures.
Set to be strategically positioned near TSMC's upcoming Fab 21 complex in Arizona, Amkor's Peoria facility will occupy 55 acres and, when fully completed, will feature over 500,000 square feet (46,451 square meters) of cleanroom space, more than twice the size of Amkor's advanced packaging site in Vietnam. Although the company has not disclosed the exact capacity or the specific technologies the facility will support, it is expected to cater to a wide range of industries, including automotive, high-performance computing, and mobile technologies. This suggests the new plant will offer diverse packaging solutions, including traditional, 2.5D, and 3D technologies.
Amkor has collaborated extensively with Apple on the vision and initial setup of the Peoria facility, as Apple is slated to be the facility's first and largest customer, marking a significant commitment from the tech giant. This partnership highlights the importance of the new facility in reinforcing the U.S. semiconductor supply chain and positioning Amkor as a key partner for companies relying on TSMC's manufacturing capabilities. The project is expected to generate around 2,000 jobs and is scheduled to begin operations in 2027.
SK hynix to Build HBM4 in the U.S.
This week SK hynix also signed a preliminary agreement with the U.S. government to receive up to $450 million in direct funding and $500 million in loans to build an advanced memory packaging facility in West Lafayette, Indiana.
The proposed facility is scheduled to begin operations in 2028, which means that it will assemble HBM4 or HBM4E memory. Meanwhile, DRAM devices for high bandwidth memory (HBM) stacks will still be produced in South Korea. Nonetheless, packing finished HBM4/HBM4E in the U.S. and possibly integrating these memory modules with high-end processors is a big deal.
In addition to building its packaging plant, SK hynix plans to collaborate with Purdue University and other local research institutions to advance semiconductor technology and packaging innovations. This partnership is intended to bolster research and development in the region, positioning the facility as a hub for AI technology and skilled employment.
Semiconductors
Kioxia Demonstrates Optical Interface SSDs for Data Centers 
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
![](https://twitter.com/share?url=https://compbuddey.blogspot.com/2024/08/intel-to-launch-lunar-lake-core-ultra.html&text=Intel to Launch "Lunar Lake" Core Ultra Chips on September 3rd <p align="center"><a href="https://www.anandtech.com/show/21494/intel-to-launch-lunar-lake-core-ultra-chips-on-september-3rd"><img src="https://images.anandtech.com/doci/21494/newsroom-core-ultra-series2_crop_575px.jpg" alt="" /></a></p><p><p>Intel’s next-generation Core Ultra laptop chips finally have a launch date: <a href="https://www.intel.com/content/www/us/en/newsroom/news/media-alert-intels-next-gen-core-ultra-launch-event.html">September 3<sup>rd</sup></a>.</p>
<p>Codenamed Lunar Lake, Intel has been touting the chips for nearly a year now. Most recently, Intel offered the press a <a href="https://www.anandtech.com/show/21425/intel-lunar-lake-architecture-deep-dive-lion-cove-xe2-and-npu4">deep dive briefing on the chips</a> and their underlying architectures at Computex back in June, along with a public preview during the company’s Computex keynote. At the time Intel was preparing for Q3’2024 launch, and that window has finally been narrowed down to a single date – September 3<sup>rd</sup> – when Intel will be hosting their Lunar Lake launch event ahead of IFA.</p>
<p>Intel’s second stab at a high volume chiplet-based processor for laptop users, Lunar Lake is aimed particularly at ultrabooks and other low-power mobile devices, with Intel looking to wrestle back the title of the most efficient PC laptop SoC. Lunar Lake is significant in this respect as Intel has never previously developed a whole chip architecture specifically for low power mobile devices before – it’s always been a scaled-down version of a wider-range architecture, such as the current Meteor Lake (Core Ultra 100 series). Consequently, Intel has been touting that they’ve made some serious efficiency advancements with their highly targeted chip, which they believe will vault them over the competition.</p>
<p align="center"><a href="https://www.anandtech.com/show/21494/intel-to-launch-lunar-lake-core-ultra-chips-on-september-3rd"><img alt="" src="https://images.anandtech.com/doci/21494/2024-06-03%2020_38_29_575px.jpg" /></a></p>
<p>All told, Lunar Lake is slated to bring a significant series of updates to Intel’s chip architectures and chip design strategies. Of particular interest is the switch to on-package LPDDR5X memory, which is a first for a high-volume Core chip. As well, Lunar Lake incorporates updated versions of virtually every one of Intel’s architecture, from the CPU P and E cores – Lion Cove and Skymont respectively – to the Xe2 GPU and 4<sup>th</sup> generation NPU (aptly named NPU 4). And, in a scandalous twist, both of the chiplets/tiles on the CPU are being made by TSMC. Intel isn’t providing any of the active silicon for the chip – though they are providing the Foveros packaging needed to put it together.</p>
<table border="0" style="text-align:center" width="95%">
<tbody>
<tr class="tgrey">
<td colspan="6">Intel CPU Architecture Generations</td>
</tr>
<tr class="tlblue">
<td> </td>
<td>Alder/Raptor Lake</td>
<td>Meteor<br />
Lake</td>
<td><b>Lunar<br />
Lake</b></td>
<td>Arrow<br />
Lake</td>
<td>Panther<br />
Lake</td>
</tr>
<tr>
<td class="tlgrey">P-Core Architecture</td>
<td>Golden Cove/<br />
Raptor Cove</td>
<td>Redwood Cove</td>
<td><strong>Lion Cove</strong></td>
<td>Lion Cove</td>
<td>Cougar Cove?</td>
</tr>
<tr>
<td class="tlgrey">E-Core Architecture</td>
<td>Gracemont</td>
<td>Crestmont</td>
<td><strong>Skymont</strong></td>
<td>Crestmont?</td>
<td>Darkmont?</td>
</tr>
<tr>
<td class="tlgrey">GPU Architecture</td>
<td>Xe-LP</td>
<td>Xe-LPG</td>
<td><strong>Xe2</strong></td>
<td>Xe2?</td>
<td>?</td>
</tr>
<tr>
<td class="tlgrey">NPU Architecture</td>
<td>N/A</td>
<td>NPU 3720</td>
<td><strong>NPU 4</strong></td>
<td>?</td>
<td>?</td>
</tr>
<tr>
<td class="tlgrey">Active Tiles</td>
<td>1 (Monolithic)</td>
<td>4</td>
<td><strong>2</strong></td>
<td>4?</td>
<td>?</td>
</tr>
<tr>
<td class="tlgrey">Manufacturing Processes</td>
<td>Intel 7</td>
<td>Intel 4 + TSMC N6 + TSMC N5</td>
<td><strong>TSMC N3B + TSMC N6</strong></td>
<td>Intel 20A + More</td>
<td>Intel 18A</td>
</tr>
<tr>
<td class="tlgrey">Segment</td>
<td>Mobile + Desktop</td>
<td>Mobile</td>
<td><strong>LP Mobile</strong></td>
<td>HP Mobile + Desktop</td>
<td>Mobile?</td>
</tr>
<tr>
<td class="tlgrey">Release Date (OEM)</td>
<td>Q4'2021</td>
<td>Q4'2023</td>
<td><strong>Q3'2024</strong></td>
<td>Q4'2024</td>
<td>2025</td>
</tr>
</tbody>
</table>
<p>Suffice it to say, no matter what happens, Lunar Lake and the Core Ultra 200 series should prove to be an interesting launch.</p>
<p>It’s worth noting, however, that while Intel’s announcement of their livestreamed event is being labeled a “launch event&rd... CPUs){kind=link}
![](https://www.pinterest.com/pin/create/button/?url=https://compbuddey.blogspot.com/2024/08/intel-to-launch-lunar-lake-core-ultra.html&media=https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_sVk3KIEwY3cb79dyOkJPdGOVleGFBpr1OBKkeBo_UuHchMhKIfq0ByK3CzROgVRcwGpWLJTqojUFrsnBvNIsYCP_9nEd7qm7fwO4aFdHUrsxTI9ZHUEG8uYVLEb2dI87fAwAGDC-qN5kf5Be8TU4SoR0R8Sic&description=Intel to Launch "Lunar Lake" Core Ultra Chips on September 3rd <p align="center"><a href="https://www.anandtech.com/show/21494/intel-to-launch-lunar-lake-core-ultra-chips-on-september-3rd"><img src="https://images.anandtech.com/doci/21494/newsroom-core-ultra-series2_crop_575px.jpg" alt="" /></a></p><p><p>Intel’s next-generation Core Ultra laptop chips finally have a launch date: <a href="https://www.intel.com/content/www/us/en/newsroom/news/media-alert-intels-next-gen-core-ultra-launch-event.html">September 3<sup>rd</sup></a>.</p>
<p>Codenamed Lunar Lake, Intel has been touting the chips for nearly a year now. Most recently, Intel offered the press a <a href="https://www.anandtech.com/show/21425/intel-lunar-lake-architecture-deep-dive-lion-cove-xe2-and-npu4">deep dive briefing on the chips</a> and their underlying architectures at Computex back in June, along with a public preview during the company’s Computex keynote. At the time Intel was preparing for Q3’2024 launch, and that window has finally been narrowed down to a single date – September 3<sup>rd</sup> – when Intel will be hosting their Lunar Lake launch event ahead of IFA.</p>
<p>Intel’s second stab at a high volume chiplet-based processor for laptop users, Lunar Lake is aimed particularly at ultrabooks and other low-power mobile devices, with Intel looking to wrestle back the title of the most efficient PC laptop SoC. Lunar Lake is significant in this respect as Intel has never previously developed a whole chip architecture specifically for low power mobile devices before – it’s always been a scaled-down version of a wider-range architecture, such as the current Meteor Lake (Core Ultra 100 series). Consequently, Intel has been touting that they’ve made some serious efficiency advancements with their highly targeted chip, which they believe will vault them over the competition.</p>
<p align="center"><a href="https://www.anandtech.com/show/21494/intel-to-launch-lunar-lake-core-ultra-chips-on-september-3rd"><img alt="" src="https://images.anandtech.com/doci/21494/2024-06-03%2020_38_29_575px.jpg" /></a></p>
<p>All told, Lunar Lake is slated to bring a significant series of updates to Intel’s chip architectures and chip design strategies. Of particular interest is the switch to on-package LPDDR5X memory, which is a first for a high-volume Core chip. As well, Lunar Lake incorporates updated versions of virtually every one of Intel’s architecture, from the CPU P and E cores – Lion Cove and Skymont respectively – to the Xe2 GPU and 4<sup>th</sup> generation NPU (aptly named NPU 4). And, in a scandalous twist, both of the chiplets/tiles on the CPU are being made by TSMC. Intel isn’t providing any of the active silicon for the chip – though they are providing the Foveros packaging needed to put it together.</p>
<table border="0" style="text-align:center" width="95%">
<tbody>
<tr class="tgrey">
<td colspan="6">Intel CPU Architecture Generations</td>
</tr>
<tr class="tlblue">
<td> </td>
<td>Alder/Raptor Lake</td>
<td>Meteor<br />
Lake</td>
<td><b>Lunar<br />
Lake</b></td>
<td>Arrow<br />
Lake</td>
<td>Panther<br />
Lake</td>
</tr>
<tr>
<td class="tlgrey">P-Core Architecture</td>
<td>Golden Cove/<br />
Raptor Cove</td>
<td>Redwood Cove</td>
<td><strong>Lion Cove</strong></td>
<td>Lion Cove</td>
<td>Cougar Cove?</td>
</tr>
<tr>
<td class="tlgrey">E-Core Architecture</td>
<td>Gracemont</td>
<td>Crestmont</td>
<td><strong>Skymont</strong></td>
<td>Crestmont?</td>
<td>Darkmont?</td>
</tr>
<tr>
<td class="tlgrey">GPU Architecture</td>
<td>Xe-LP</td>
<td>Xe-LPG</td>
<td><strong>Xe2</strong></td>
<td>Xe2?</td>
<td>?</td>
</tr>
<tr>
<td class="tlgrey">NPU Architecture</td>
<td>N/A</td>
<td>NPU 3720</td>
<td><strong>NPU 4</strong></td>
<td>?</td>
<td>?</td>
</tr>
<tr>
<td class="tlgrey">Active Tiles</td>
<td>1 (Monolithic)</td>
<td>4</td>
<td><strong>2</strong></td>
<td>4?</td>
<td>?</td>
</tr>
<tr>
<td class="tlgrey">Manufacturing Processes</td>
<td>Intel 7</td>
<td>Intel 4 + TSMC N6 + TSMC N5</td>
<td><strong>TSMC N3B + TSMC N6</strong></td>
<td>Intel 20A + More</td>
<td>Intel 18A</td>
</tr>
<tr>
<td class="tlgrey">Segment</td>
<td>Mobile + Desktop</td>
<td>Mobile</td>
<td><strong>LP Mobile</strong></td>
<td>HP Mobile + Desktop</td>
<td>Mobile?</td>
</tr>
<tr>
<td class="tlgrey">Release Date (OEM)</td>
<td>Q4'2021</td>
<td>Q4'2023</td>
<td><strong>Q3'2024</strong></td>
<td>Q4'2024</td>
<td>2025</td>
</tr>
</tbody>
</table>
<p>Suffice it to say, no matter what happens, Lunar Lake and the Core Ultra 200 series should prove to be an interesting launch.</p>
<p>It’s worth noting, however, that while Intel’s announcement of their livestreamed event is being labeled a “launch event&rd... CPUs){kind=link}
![](https://web.whatsapp.com/send?text=Intel to Launch "Lunar Lake" Core Ultra Chips on September 3rd <p align="center"><a href="https://www.anandtech.com/show/21494/intel-to-launch-lunar-lake-core-ultra-chips-on-september-3rd"><img src="https://images.anandtech.com/doci/21494/newsroom-core-ultra-series2_crop_575px.jpg" alt="" /></a></p><p><p>Intel’s next-generation Core Ultra laptop chips finally have a launch date: <a href="https://www.intel.com/content/www/us/en/newsroom/news/media-alert-intels-next-gen-core-ultra-launch-event.html">September 3<sup>rd</sup></a>.</p>
<p>Codenamed Lunar Lake, Intel has been touting the chips for nearly a year now. Most recently, Intel offered the press a <a href="https://www.anandtech.com/show/21425/intel-lunar-lake-architecture-deep-dive-lion-cove-xe2-and-npu4">deep dive briefing on the chips</a> and their underlying architectures at Computex back in June, along with a public preview during the company’s Computex keynote. At the time Intel was preparing for Q3’2024 launch, and that window has finally been narrowed down to a single date – September 3<sup>rd</sup> – when Intel will be hosting their Lunar Lake launch event ahead of IFA.</p>
<p>Intel’s second stab at a high volume chiplet-based processor for laptop users, Lunar Lake is aimed particularly at ultrabooks and other low-power mobile devices, with Intel looking to wrestle back the title of the most efficient PC laptop SoC. Lunar Lake is significant in this respect as Intel has never previously developed a whole chip architecture specifically for low power mobile devices before – it’s always been a scaled-down version of a wider-range architecture, such as the current Meteor Lake (Core Ultra 100 series). Consequently, Intel has been touting that they’ve made some serious efficiency advancements with their highly targeted chip, which they believe will vault them over the competition.</p>
<p align="center"><a href="https://www.anandtech.com/show/21494/intel-to-launch-lunar-lake-core-ultra-chips-on-september-3rd"><img alt="" src="https://images.anandtech.com/doci/21494/2024-06-03%2020_38_29_575px.jpg" /></a></p>
<p>All told, Lunar Lake is slated to bring a significant series of updates to Intel’s chip architectures and chip design strategies. Of particular interest is the switch to on-package LPDDR5X memory, which is a first for a high-volume Core chip. As well, Lunar Lake incorporates updated versions of virtually every one of Intel’s architecture, from the CPU P and E cores – Lion Cove and Skymont respectively – to the Xe2 GPU and 4<sup>th</sup> generation NPU (aptly named NPU 4). And, in a scandalous twist, both of the chiplets/tiles on the CPU are being made by TSMC. Intel isn’t providing any of the active silicon for the chip – though they are providing the Foveros packaging needed to put it together.</p>
<table border="0" style="text-align:center" width="95%">
<tbody>
<tr class="tgrey">
<td colspan="6">Intel CPU Architecture Generations</td>
</tr>
<tr class="tlblue">
<td> </td>
<td>Alder/Raptor Lake</td>
<td>Meteor<br />
Lake</td>
<td><b>Lunar<br />
Lake</b></td>
<td>Arrow<br />
Lake</td>
<td>Panther<br />
Lake</td>
</tr>
<tr>
<td class="tlgrey">P-Core Architecture</td>
<td>Golden Cove/<br />
Raptor Cove</td>
<td>Redwood Cove</td>
<td><strong>Lion Cove</strong></td>
<td>Lion Cove</td>
<td>Cougar Cove?</td>
</tr>
<tr>
<td class="tlgrey">E-Core Architecture</td>
<td>Gracemont</td>
<td>Crestmont</td>
<td><strong>Skymont</strong></td>
<td>Crestmont?</td>
<td>Darkmont?</td>
</tr>
<tr>
<td class="tlgrey">GPU Architecture</td>
<td>Xe-LP</td>
<td>Xe-LPG</td>
<td><strong>Xe2</strong></td>
<td>Xe2?</td>
<td>?</td>
</tr>
<tr>
<td class="tlgrey">NPU Architecture</td>
<td>N/A</td>
<td>NPU 3720</td>
<td><strong>NPU 4</strong></td>
<td>?</td>
<td>?</td>
</tr>
<tr>
<td class="tlgrey">Active Tiles</td>
<td>1 (Monolithic)</td>
<td>4</td>
<td><strong>2</strong></td>
<td>4?</td>
<td>?</td>
</tr>
<tr>
<td class="tlgrey">Manufacturing Processes</td>
<td>Intel 7</td>
<td>Intel 4 + TSMC N6 + TSMC N5</td>
<td><strong>TSMC N3B + TSMC N6</strong></td>
<td>Intel 20A + More</td>
<td>Intel 18A</td>
</tr>
<tr>
<td class="tlgrey">Segment</td>
<td>Mobile + Desktop</td>
<td>Mobile</td>
<td><strong>LP Mobile</strong></td>
<td>HP Mobile + Desktop</td>
<td>Mobile?</td>
</tr>
<tr>
<td class="tlgrey">Release Date (OEM)</td>
<td>Q4'2021</td>
<td>Q4'2023</td>
<td><strong>Q3'2024</strong></td>
<td>Q4'2024</td>
<td>2025</td>
</tr>
</tbody>
</table>
<p>Suffice it to say, no matter what happens, Lunar Lake and the Core Ultra 200 series should prove to be an interesting launch.</p>
<p>It’s worth noting, however, that while Intel’s announcement of their livestreamed event is being labeled a “launch event&rd... CPUs | https://compbuddey.blogspot.com/2024/08/intel-to-launch-lunar-lake-core-ultra.html){kind=link}
![](mailto:?subject=Intel to Launch "Lunar Lake" Core Ultra Chips on September 3rd <p align="center"><a href="https://www.anandtech.com/show/21494/intel-to-launch-lunar-lake-core-ultra-chips-on-september-3rd"><img src="https://images.anandtech.com/doci/21494/newsroom-core-ultra-series2_crop_575px.jpg" alt="" /></a></p><p><p>Intel’s next-generation Core Ultra laptop chips finally have a launch date: <a href="https://www.intel.com/content/www/us/en/newsroom/news/media-alert-intels-next-gen-core-ultra-launch-event.html">September 3<sup>rd</sup></a>.</p>
<p>Codenamed Lunar Lake, Intel has been touting the chips for nearly a year now. Most recently, Intel offered the press a <a href="https://www.anandtech.com/show/21425/intel-lunar-lake-architecture-deep-dive-lion-cove-xe2-and-npu4">deep dive briefing on the chips</a> and their underlying architectures at Computex back in June, along with a public preview during the company’s Computex keynote. At the time Intel was preparing for Q3’2024 launch, and that window has finally been narrowed down to a single date – September 3<sup>rd</sup> – when Intel will be hosting their Lunar Lake launch event ahead of IFA.</p>
<p>Intel’s second stab at a high volume chiplet-based processor for laptop users, Lunar Lake is aimed particularly at ultrabooks and other low-power mobile devices, with Intel looking to wrestle back the title of the most efficient PC laptop SoC. Lunar Lake is significant in this respect as Intel has never previously developed a whole chip architecture specifically for low power mobile devices before – it’s always been a scaled-down version of a wider-range architecture, such as the current Meteor Lake (Core Ultra 100 series). Consequently, Intel has been touting that they’ve made some serious efficiency advancements with their highly targeted chip, which they believe will vault them over the competition.</p>
<p align="center"><a href="https://www.anandtech.com/show/21494/intel-to-launch-lunar-lake-core-ultra-chips-on-september-3rd"><img alt="" src="https://images.anandtech.com/doci/21494/2024-06-03%2020_38_29_575px.jpg" /></a></p>
<p>All told, Lunar Lake is slated to bring a significant series of updates to Intel’s chip architectures and chip design strategies. Of particular interest is the switch to on-package LPDDR5X memory, which is a first for a high-volume Core chip. As well, Lunar Lake incorporates updated versions of virtually every one of Intel’s architecture, from the CPU P and E cores – Lion Cove and Skymont respectively – to the Xe2 GPU and 4<sup>th</sup> generation NPU (aptly named NPU 4). And, in a scandalous twist, both of the chiplets/tiles on the CPU are being made by TSMC. Intel isn’t providing any of the active silicon for the chip – though they are providing the Foveros packaging needed to put it together.</p>
<table border="0" style="text-align:center" width="95%">
<tbody>
<tr class="tgrey">
<td colspan="6">Intel CPU Architecture Generations</td>
</tr>
<tr class="tlblue">
<td> </td>
<td>Alder/Raptor Lake</td>
<td>Meteor<br />
Lake</td>
<td><b>Lunar<br />
Lake</b></td>
<td>Arrow<br />
Lake</td>
<td>Panther<br />
Lake</td>
</tr>
<tr>
<td class="tlgrey">P-Core Architecture</td>
<td>Golden Cove/<br />
Raptor Cove</td>
<td>Redwood Cove</td>
<td><strong>Lion Cove</strong></td>
<td>Lion Cove</td>
<td>Cougar Cove?</td>
</tr>
<tr>
<td class="tlgrey">E-Core Architecture</td>
<td>Gracemont</td>
<td>Crestmont</td>
<td><strong>Skymont</strong></td>
<td>Crestmont?</td>
<td>Darkmont?</td>
</tr>
<tr>
<td class="tlgrey">GPU Architecture</td>
<td>Xe-LP</td>
<td>Xe-LPG</td>
<td><strong>Xe2</strong></td>
<td>Xe2?</td>
<td>?</td>
</tr>
<tr>
<td class="tlgrey">NPU Architecture</td>
<td>N/A</td>
<td>NPU 3720</td>
<td><strong>NPU 4</strong></td>
<td>?</td>
<td>?</td>
</tr>
<tr>
<td class="tlgrey">Active Tiles</td>
<td>1 (Monolithic)</td>
<td>4</td>
<td><strong>2</strong></td>
<td>4?</td>
<td>?</td>
</tr>
<tr>
<td class="tlgrey">Manufacturing Processes</td>
<td>Intel 7</td>
<td>Intel 4 + TSMC N6 + TSMC N5</td>
<td><strong>TSMC N3B + TSMC N6</strong></td>
<td>Intel 20A + More</td>
<td>Intel 18A</td>
</tr>
<tr>
<td class="tlgrey">Segment</td>
<td>Mobile + Desktop</td>
<td>Mobile</td>
<td><strong>LP Mobile</strong></td>
<td>HP Mobile + Desktop</td>
<td>Mobile?</td>
</tr>
<tr>
<td class="tlgrey">Release Date (OEM)</td>
<td>Q4'2021</td>
<td>Q4'2023</td>
<td><strong>Q3'2024</strong></td>
<td>Q4'2024</td>
<td>2025</td>
</tr>
</tbody>
</table>
<p>Suffice it to say, no matter what happens, Lunar Lake and the Core Ultra 200 series should prove to be an interesting launch.</p>
<p>It’s worth noting, however, that while Intel’s announcement of their livestreamed event is being labeled a “launch event&rd... CPUs&body=https://compbuddey.blogspot.com/2024/08/intel-to-launch-lunar-lake-core-ultra.html){kind=link}
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
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