Intel 18A Status Update: First Chips Booting, First External Customer Tape-Out in H1’25
Following Intel’s painful Q2 earnings call and the announcement of their 2025 cost reduction plan last week, it has become increasingly evident that Intel’s future is in the hands of their foundry group. Between Intel’s IDM 2.0 initiative and their internal chip production plans, all roads lead back to Intel retaking – and retaining – fab process leadership. To win as both a chip designer and a contract chip maker, Intel needs to be able to regain the fab technology lead it once held. In many respects it’s a return to Intel’s classic (and most successful) operating model, but never has it been so risky at it is for the already weakened Intel.
Intel’s do-or-die dash for process leadership means that, for the next 18 months or so, all eyes are on the company’s 20A and 18A process nodes. The final nodes in their ambitious 5 Nodes in 4 Years roadmap, the twinned 20A/18A are the culmination of several new technologies, primarily Intel’s GAAFET implementation (RibbonFET), which is being combined with PowerVia, Intel’s backside power delivery network (BS-PDN) technology. 20A is set to serve as Intel’s early version of the node, and 18A the refined version for long-term use both internally, and as the first major external node for Intel Foundry. To say that everything rides on Intel 18A isn’t quite accurate, but it’s only a slight embellishment.
To that end, we’re going to see Intel deliver a lot of status updates on 18A over the next year as they continue to outline to investors and external customers alike that they have the manufacturing side of their business in order. And today is one of those days, with a fresh update on the state of 18A.
18A Chips Back & Booting
So what’s new with 18A? The biggest news out of Intel this morning is that their first 18A chips are back from the development fab and are successfully booting operating systems. This means the silicon not only works (power-on), but works well enough to complete core tasks. It’s a major step in bringing up a chip, and at this point, Intel wants to make sure to let the whole world know.
Earlier this year the company finished taping out both of its lead 18A chips: Panther Lake for clients, and Clearwater Forest for servers. And it’s both chips that are booting. This is made all the more significant by the fact that Clearwater Forest also relies on Intel’s die-to-die hybrid bonding packaging technology, Foveros Direct 3D, where it will be the lead product for that technology as well. Which for Intel, is a promising sign that not only are their silicon lithography ambitions paying off, but their intention to lead in advanced packaging is on-track as well.
And while Intel doesn’t normally talk about yields this early in the game, it’s interesting to note that in a separate Q&A being published this morning with Intel Foundry’s new boss, Kevin O’Buckley, the head of Foundry Services explicitly comments that Panther Lake is “yielding well”. Similarly, Panther Lake’s DDR memory controller (a complex block mixing logic with a PHY) is already running at its target frequency. Progress is going so well, apparently, that according to O’Buckley, it’s ahead of schedule on its product qualification milestones.
PDK 1.0 Released, First External Customer Tape-Out Expected in H1’25
As for Intel’s contract foundry business, the company is ramping up its efforts there now that the first full process design kit (PDK) is ready for 18A. Intel released their 18A PDK 1.0 last month, giving Intel’s customers (and potential customers) the tools to finally finish designing their chips for production. As is typically the case of a new node, pre-release PDKs were available for companies to get start... CPUs
Posted by The Techinical Support
Western Digital Introduces 4 TB microSDUC, 8 TB SDUC, and 16 TB External SSDs 
Western Digital's BiCS8 218-layer 3D NAND is being put to good use in a wide range of client and enterprise platforms, including WD's upcoming Gen 5 client SSDs and 128 TB-class datacenter SSD. On the external storage front, the company demonstrated four different products: for card-based media, 4 TB microSDUC and 8 TB SDUC cards with UHS-I speeds, and on the portable SSD front we had two 16 TB drives. One will be a SanDisk Desk Drive with external power, and the other in the SanDisk Extreme Pro housing with a lanyard opening in the case.
All of these are using BiCS8 QLC NAND, though I did hear booth talk (as I was taking leave) that they were not supposed to divulge the use of QLC in these products. The 4 TB microSDUC and 8 TB SDUC cards are rated for UHS-I speeds. They are being marketed under the SanDisk Ultra branding.
The SanDisk Desk Drive is an external SSD with a 18W power adapter, and it has been in the market for a few months now. Initially launched in capacities up to 8 TB, Western Digital had promised a 16 TB version before the end of the year. It appears that the product is coming to retail quite soon. One aspect to note is that this drive has been using TLC for the SKUs that are currently in the market, so it appears unlikely that the 16 TB version would be QLC. The units (at least up to the 8 TB capacity point) come with two SN850XE drives. Given the recent introduction of the 8 TB SN850X, an 'E' version with tweaked firmware is likely to be present in the 16 TB Desk Drive.
The 16 TB portable SSD in the SanDisk Extreme housing was a technology demonstration. It is definitely the highest capacity bus-powered portable SSD demonstrated by any vendor at any trade show thus far. Given the 16 TB Desk Drive's imminent market introduction, it is just a matter of time before the technology demonstration of the bus-powered version becomes a retail reality.
Storage
Solidigm 122 TB Enterprise QLC SSD Announced for Early 2025 Release 
Solidigm's D5-P5336 61.44 TB enterprise QLC SSD released in mid-2023 has seen unprecedented demand over the last few quarters, driven by the insatiable demand for high-capacity storage in AI datacenters. Multiple vendors have recognized and started preparing products to service this demand, but Solidigm appears to have taken the lead in actual market availability.
At FMS 2024, Solidigm previewed a U.2 version of their upcoming 122 TB enterprise QLC SSD. The proof-of-concept Gen 4 drives were running live in a 2U server, and Solidigm is preparing them for an early 2025 release.
Given the capacity play, Solidigm will be relying on QLC technology. However, the company was coy about confirming the NAND generation used in the product.
Source: The Advantages of Floating Gate Technology (YouTube)
The 61.44 TB D5-P5336 currently utilizes Solidigm's 192L 3D QLC based on the floating gate architecture. This has a distinct advantage for QLC endurance compared to the charge trap architecture also available to Solidigm from SK hynix. That said, SK hynix's 238L NAND also has a QLC avatar, which gives Solidigm the flexibility to use either NAND for the production version of the 122 TB drive. Solidigm expects to confirm this by the end of year in preparation for volume shipment in the first half of 2025.
Storage
Source: The Advantages of Floating Gate Technology (YouTube)
Western Digital Introduces 4 TB microSDUC, 8 TB SDUC, and 16 TB External SSDs
Western Digital's BiCS8 218-layer 3D NAND is being put to good use in a wide range of client and enterprise platforms, including WD's upcoming Gen 5 client SSDs and 128 TB-class datacenter SSD. On the external storage front, the company demonstrated four different products: for card-based media, 4 TB microSDUC and 8 TB SDUC cards with UHS-I speeds, and on the portable SSD front we had two 16 TB drives. One will be a SanDisk Desk Drive with external power, and the other in the SanDisk Extreme Pro housing with a lanyard opening in the case.
All of these are using BiCS8 QLC NAND, though I did hear booth talk (as I was taking leave) that they were not supposed to divulge the use of QLC in these products. The 4 TB microSDUC and 8 TB SDUC cards are rated for UHS-I speeds. They are being marketed under the SanDisk Ultra branding.
The SanDisk Desk Drive is an external SSD with a 18W power adapter, and it has been in the market for a few months now. Initially launched in capacities up to 8 TB, Western Digital had promised a 16 TB version before the end of the year. It appears that the product is coming to retail quite soon. One aspect to note is that this drive has been using TLC for the SKUs that are currently in the market, so it appears unlikely that the 16 TB version would be QLC. The units (at least up to the 8 TB capacity point) come with two SN850XE drives. Given the recent introduction of the 8 TB SN850X, an 'E' version with tweaked firmware is likely to be present in the 16 TB Desk Drive.
The 16 TB portable SSD in the SanDisk Extreme housing was a technology demonstration. It is definitely the highest capacity bus-powered portable SSD demonstrated by any vendor at any trade show thus far. Given the 16 TB Desk Drive's imminent market introduction, it is just a matter of time before the technology demonstration of the bus-powered version becomes a retail reality.
Storage
Solidigm 122 TB Enterprise QLC SSD Announced for Early 2025 Release
Solidigm's D5-P5336 61.44 TB enterprise QLC SSD released in mid-2023 has seen unprecedented demand over the last few quarters, driven by the insatiable demand for high-capacity storage in AI datacenters. Multiple vendors have recognized and started preparing products to service this demand, but Solidigm appears to have taken the lead in actual market availability.
At FMS 2024, Solidigm previewed a U.2 version of their upcoming 122 TB enterprise QLC SSD. The proof-of-concept Gen 4 drives were running live in a 2U server, and Solidigm is preparing them for an early 2025 release.
Given the capacity play, Solidigm will be relying on QLC technology. However, the company was coy about confirming the NAND generation used in the product.
Source: The Advantages of Floating Gate Technology (YouTube)
The 61.44 TB D5-P5336 currently utilizes Solidigm's 192L 3D QLC based on the floating gate architecture. This has a distinct advantage for QLC endurance compared to the charge trap architecture also available to Solidigm from SK hynix. That said, SK hynix's 238L NAND also has a QLC avatar, which gives Solidigm the flexibility to use either NAND for the production version of the 122 TB drive. Solidigm expects to confirm this by the end of year in preparation for volume shipment in the first half of 2025.
Storage
Source: The Advantages of Floating Gate Technology (YouTube)
![](https://twitter.com/share?url=https://compbuddey.blogspot.com/2024/08/intel-18a-status-update-first-chips_16.html&text=Intel 18A Status Update: First Chips Booting, First External Customer Tape-Out in H1’25 <p align="center"><a href="https://www.anandtech.com/show/21504/intel-18a-status-update-first-chips-booting-first-external-customer-tapeout-in-h125"><img src="https://images.anandtech.com/doci/21504/intel-18a-wafer-2_575px.jpg" alt="" /></a></p><p><p>Following Intel’s painful Q2 earnings call and the announcement of their <a href="https://www.anandtech.com/show/21496/intel-bleeds-red-plans-15-workforce-layoff-and-10b-cuts-for-2025">2025 cost reduction plan</a> last week, it has become increasingly evident that Intel’s future is in the hands of their foundry group. Between Intel’s IDM 2.0 initiative and their internal chip production plans, all roads lead back to Intel retaking – and retaining – fab process leadership. To win as both a chip designer and a contract chip maker, Intel needs to be able to regain the fab technology lead it once held. In many respects it’s a return to Intel’s classic (and most successful) operating model, but never has it been so risky at it is for the already weakened Intel.</p>
<p>Intel’s do-or-die dash for process leadership means that, for the next 18 months or so, all eyes are on the company’s 20A and 18A process nodes. The final nodes in their ambitious 5 Nodes in 4 Years roadmap, the twinned 20A/18A are the culmination of several new technologies, primarily Intel’s GAAFET implementation (RibbonFET), which is being combined with PowerVia, Intel’s backside power delivery network (BS-PDN) technology. 20A is set to serve as Intel’s early version of the node, and 18A the refined version for long-term use both internally, and as the first major external node for Intel Foundry. To say that everything rides on Intel 18A isn’t quite accurate, but it’s only a slight embellishment.</p>
<p>To that end, we’re going to see Intel deliver a lot of status updates on 18A over the next year as they continue to outline to investors and external customers alike that they have the manufacturing side of their business in order. And today is one of those days, with a fresh update on the state of 18A.</p>
<h3>18A Chips Back & Booting</h3>
<p>So what’s new with 18A? The biggest news out of Intel this morning is that their first 18A chips are back from the development fab and are successfully booting operating systems. This means the silicon not only works (power-on), but works well enough to complete core tasks. It’s a major step in bringing up a chip, and at this point, Intel wants to make sure to let the whole world know.</p>
<p align="center"><a href="https://www.anandtech.com/show/21504/intel-18a-status-update-first-chips-booting-first-external-customer-tapeout-in-h125"><img alt="" src="https://images.anandtech.com/doci/21504/2024-Q3-Progress-on-Foundry_18A_Aug62024.png" style="width: 100%;" /></a></p>
<p>Earlier this year the company finished taping out both of its lead 18A chips: <a href="https://www.anandtech.com/show/21430/update-on-intel-s-panther-lake-at-computex-2024-intel-powering-up-intel-18a-wafer-next-week">Panther Lake</a> for clients, and <a href="https://www.anandtech.com/show/18797/intel-updates-data-center-roadmap-xeons-on-track-emerald-in-q423-sierra-forest-in-h124">Clearwater Forest</a> for servers. And it’s both chips that are booting. This is made all the more significant by the fact that Clearwater Forest also relies on Intel’s die-to-die hybrid bonding packaging technology, Foveros Direct 3D, where it will be the lead product for that technology as well. Which for Intel, is a promising sign that not only are their silicon lithography ambitions paying off, but their intention to lead in advanced packaging is on-track as well.</p>
<p>And while Intel doesn’t normally talk about yields this early in the game, it’s interesting to note that in a separate Q&A being published this morning with Intel Foundry’s new boss, <a href="https://www.intel.com/content/www/us/en/newsroom/news/kevin-obuckley-talks-progress-intel-18a.html">Kevin O’Buckley</a>, the head of Foundry Services explicitly comments that Panther Lake is “yielding well”. Similarly, Panther Lake’s DDR memory controller (a complex block mixing logic with a PHY) is already running at its target frequency. Progress is going so well, apparently, that according to O’Buckley, it’s ahead of schedule on its product qualification milestones.</p>
<h3>PDK 1.0 Released, First External Customer Tape-Out Expected in H1’25</h3>
<p>As for Intel’s contract foundry business, the company is ramping up its efforts there now that the first full process design kit (PDK) is ready for 18A. Intel released their 18A PDK 1.0 last month, giving Intel’s customers (and potential customers) the tools to finally finish designing their chips for production. As is typically the case of a new node, pre-release PDKs were available for companies to get start... CPUs){kind=link}
![](https://www.pinterest.com/pin/create/button/?url=https://compbuddey.blogspot.com/2024/08/intel-18a-status-update-first-chips_16.html&media=https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_sa5uzbVnjrCOFoAnX2n6dbiC9aWKxB30GrEWhdXj701NO2aeCN30W-VZq4BoRvQeq97SBie8YhHuhhpf73hcFXWDGhEn1nPqPlWpl6_hbS4Q1_9F8QlDiBB0gxPROmPsy0olelMA&description=Intel 18A Status Update: First Chips Booting, First External Customer Tape-Out in H1’25 <p align="center"><a href="https://www.anandtech.com/show/21504/intel-18a-status-update-first-chips-booting-first-external-customer-tapeout-in-h125"><img src="https://images.anandtech.com/doci/21504/intel-18a-wafer-2_575px.jpg" alt="" /></a></p><p><p>Following Intel’s painful Q2 earnings call and the announcement of their <a href="https://www.anandtech.com/show/21496/intel-bleeds-red-plans-15-workforce-layoff-and-10b-cuts-for-2025">2025 cost reduction plan</a> last week, it has become increasingly evident that Intel’s future is in the hands of their foundry group. Between Intel’s IDM 2.0 initiative and their internal chip production plans, all roads lead back to Intel retaking – and retaining – fab process leadership. To win as both a chip designer and a contract chip maker, Intel needs to be able to regain the fab technology lead it once held. In many respects it’s a return to Intel’s classic (and most successful) operating model, but never has it been so risky at it is for the already weakened Intel.</p>
<p>Intel’s do-or-die dash for process leadership means that, for the next 18 months or so, all eyes are on the company’s 20A and 18A process nodes. The final nodes in their ambitious 5 Nodes in 4 Years roadmap, the twinned 20A/18A are the culmination of several new technologies, primarily Intel’s GAAFET implementation (RibbonFET), which is being combined with PowerVia, Intel’s backside power delivery network (BS-PDN) technology. 20A is set to serve as Intel’s early version of the node, and 18A the refined version for long-term use both internally, and as the first major external node for Intel Foundry. To say that everything rides on Intel 18A isn’t quite accurate, but it’s only a slight embellishment.</p>
<p>To that end, we’re going to see Intel deliver a lot of status updates on 18A over the next year as they continue to outline to investors and external customers alike that they have the manufacturing side of their business in order. And today is one of those days, with a fresh update on the state of 18A.</p>
<h3>18A Chips Back & Booting</h3>
<p>So what’s new with 18A? The biggest news out of Intel this morning is that their first 18A chips are back from the development fab and are successfully booting operating systems. This means the silicon not only works (power-on), but works well enough to complete core tasks. It’s a major step in bringing up a chip, and at this point, Intel wants to make sure to let the whole world know.</p>
<p align="center"><a href="https://www.anandtech.com/show/21504/intel-18a-status-update-first-chips-booting-first-external-customer-tapeout-in-h125"><img alt="" src="https://images.anandtech.com/doci/21504/2024-Q3-Progress-on-Foundry_18A_Aug62024.png" style="width: 100%;" /></a></p>
<p>Earlier this year the company finished taping out both of its lead 18A chips: <a href="https://www.anandtech.com/show/21430/update-on-intel-s-panther-lake-at-computex-2024-intel-powering-up-intel-18a-wafer-next-week">Panther Lake</a> for clients, and <a href="https://www.anandtech.com/show/18797/intel-updates-data-center-roadmap-xeons-on-track-emerald-in-q423-sierra-forest-in-h124">Clearwater Forest</a> for servers. And it’s both chips that are booting. This is made all the more significant by the fact that Clearwater Forest also relies on Intel’s die-to-die hybrid bonding packaging technology, Foveros Direct 3D, where it will be the lead product for that technology as well. Which for Intel, is a promising sign that not only are their silicon lithography ambitions paying off, but their intention to lead in advanced packaging is on-track as well.</p>
<p>And while Intel doesn’t normally talk about yields this early in the game, it’s interesting to note that in a separate Q&A being published this morning with Intel Foundry’s new boss, <a href="https://www.intel.com/content/www/us/en/newsroom/news/kevin-obuckley-talks-progress-intel-18a.html">Kevin O’Buckley</a>, the head of Foundry Services explicitly comments that Panther Lake is “yielding well”. Similarly, Panther Lake’s DDR memory controller (a complex block mixing logic with a PHY) is already running at its target frequency. Progress is going so well, apparently, that according to O’Buckley, it’s ahead of schedule on its product qualification milestones.</p>
<h3>PDK 1.0 Released, First External Customer Tape-Out Expected in H1’25</h3>
<p>As for Intel’s contract foundry business, the company is ramping up its efforts there now that the first full process design kit (PDK) is ready for 18A. Intel released their 18A PDK 1.0 last month, giving Intel’s customers (and potential customers) the tools to finally finish designing their chips for production. As is typically the case of a new node, pre-release PDKs were available for companies to get start... CPUs){kind=link}
![](https://web.whatsapp.com/send?text=Intel 18A Status Update: First Chips Booting, First External Customer Tape-Out in H1’25 <p align="center"><a href="https://www.anandtech.com/show/21504/intel-18a-status-update-first-chips-booting-first-external-customer-tapeout-in-h125"><img src="https://images.anandtech.com/doci/21504/intel-18a-wafer-2_575px.jpg" alt="" /></a></p><p><p>Following Intel’s painful Q2 earnings call and the announcement of their <a href="https://www.anandtech.com/show/21496/intel-bleeds-red-plans-15-workforce-layoff-and-10b-cuts-for-2025">2025 cost reduction plan</a> last week, it has become increasingly evident that Intel’s future is in the hands of their foundry group. Between Intel’s IDM 2.0 initiative and their internal chip production plans, all roads lead back to Intel retaking – and retaining – fab process leadership. To win as both a chip designer and a contract chip maker, Intel needs to be able to regain the fab technology lead it once held. In many respects it’s a return to Intel’s classic (and most successful) operating model, but never has it been so risky at it is for the already weakened Intel.</p>
<p>Intel’s do-or-die dash for process leadership means that, for the next 18 months or so, all eyes are on the company’s 20A and 18A process nodes. The final nodes in their ambitious 5 Nodes in 4 Years roadmap, the twinned 20A/18A are the culmination of several new technologies, primarily Intel’s GAAFET implementation (RibbonFET), which is being combined with PowerVia, Intel’s backside power delivery network (BS-PDN) technology. 20A is set to serve as Intel’s early version of the node, and 18A the refined version for long-term use both internally, and as the first major external node for Intel Foundry. To say that everything rides on Intel 18A isn’t quite accurate, but it’s only a slight embellishment.</p>
<p>To that end, we’re going to see Intel deliver a lot of status updates on 18A over the next year as they continue to outline to investors and external customers alike that they have the manufacturing side of their business in order. And today is one of those days, with a fresh update on the state of 18A.</p>
<h3>18A Chips Back & Booting</h3>
<p>So what’s new with 18A? The biggest news out of Intel this morning is that their first 18A chips are back from the development fab and are successfully booting operating systems. This means the silicon not only works (power-on), but works well enough to complete core tasks. It’s a major step in bringing up a chip, and at this point, Intel wants to make sure to let the whole world know.</p>
<p align="center"><a href="https://www.anandtech.com/show/21504/intel-18a-status-update-first-chips-booting-first-external-customer-tapeout-in-h125"><img alt="" src="https://images.anandtech.com/doci/21504/2024-Q3-Progress-on-Foundry_18A_Aug62024.png" style="width: 100%;" /></a></p>
<p>Earlier this year the company finished taping out both of its lead 18A chips: <a href="https://www.anandtech.com/show/21430/update-on-intel-s-panther-lake-at-computex-2024-intel-powering-up-intel-18a-wafer-next-week">Panther Lake</a> for clients, and <a href="https://www.anandtech.com/show/18797/intel-updates-data-center-roadmap-xeons-on-track-emerald-in-q423-sierra-forest-in-h124">Clearwater Forest</a> for servers. And it’s both chips that are booting. This is made all the more significant by the fact that Clearwater Forest also relies on Intel’s die-to-die hybrid bonding packaging technology, Foveros Direct 3D, where it will be the lead product for that technology as well. Which for Intel, is a promising sign that not only are their silicon lithography ambitions paying off, but their intention to lead in advanced packaging is on-track as well.</p>
<p>And while Intel doesn’t normally talk about yields this early in the game, it’s interesting to note that in a separate Q&A being published this morning with Intel Foundry’s new boss, <a href="https://www.intel.com/content/www/us/en/newsroom/news/kevin-obuckley-talks-progress-intel-18a.html">Kevin O’Buckley</a>, the head of Foundry Services explicitly comments that Panther Lake is “yielding well”. Similarly, Panther Lake’s DDR memory controller (a complex block mixing logic with a PHY) is already running at its target frequency. Progress is going so well, apparently, that according to O’Buckley, it’s ahead of schedule on its product qualification milestones.</p>
<h3>PDK 1.0 Released, First External Customer Tape-Out Expected in H1’25</h3>
<p>As for Intel’s contract foundry business, the company is ramping up its efforts there now that the first full process design kit (PDK) is ready for 18A. Intel released their 18A PDK 1.0 last month, giving Intel’s customers (and potential customers) the tools to finally finish designing their chips for production. As is typically the case of a new node, pre-release PDKs were available for companies to get start... CPUs | https://compbuddey.blogspot.com/2024/08/intel-18a-status-update-first-chips_16.html){kind=link}
![](mailto:?subject=Intel 18A Status Update: First Chips Booting, First External Customer Tape-Out in H1’25 <p align="center"><a href="https://www.anandtech.com/show/21504/intel-18a-status-update-first-chips-booting-first-external-customer-tapeout-in-h125"><img src="https://images.anandtech.com/doci/21504/intel-18a-wafer-2_575px.jpg" alt="" /></a></p><p><p>Following Intel’s painful Q2 earnings call and the announcement of their <a href="https://www.anandtech.com/show/21496/intel-bleeds-red-plans-15-workforce-layoff-and-10b-cuts-for-2025">2025 cost reduction plan</a> last week, it has become increasingly evident that Intel’s future is in the hands of their foundry group. Between Intel’s IDM 2.0 initiative and their internal chip production plans, all roads lead back to Intel retaking – and retaining – fab process leadership. To win as both a chip designer and a contract chip maker, Intel needs to be able to regain the fab technology lead it once held. In many respects it’s a return to Intel’s classic (and most successful) operating model, but never has it been so risky at it is for the already weakened Intel.</p>
<p>Intel’s do-or-die dash for process leadership means that, for the next 18 months or so, all eyes are on the company’s 20A and 18A process nodes. The final nodes in their ambitious 5 Nodes in 4 Years roadmap, the twinned 20A/18A are the culmination of several new technologies, primarily Intel’s GAAFET implementation (RibbonFET), which is being combined with PowerVia, Intel’s backside power delivery network (BS-PDN) technology. 20A is set to serve as Intel’s early version of the node, and 18A the refined version for long-term use both internally, and as the first major external node for Intel Foundry. To say that everything rides on Intel 18A isn’t quite accurate, but it’s only a slight embellishment.</p>
<p>To that end, we’re going to see Intel deliver a lot of status updates on 18A over the next year as they continue to outline to investors and external customers alike that they have the manufacturing side of their business in order. And today is one of those days, with a fresh update on the state of 18A.</p>
<h3>18A Chips Back & Booting</h3>
<p>So what’s new with 18A? The biggest news out of Intel this morning is that their first 18A chips are back from the development fab and are successfully booting operating systems. This means the silicon not only works (power-on), but works well enough to complete core tasks. It’s a major step in bringing up a chip, and at this point, Intel wants to make sure to let the whole world know.</p>
<p align="center"><a href="https://www.anandtech.com/show/21504/intel-18a-status-update-first-chips-booting-first-external-customer-tapeout-in-h125"><img alt="" src="https://images.anandtech.com/doci/21504/2024-Q3-Progress-on-Foundry_18A_Aug62024.png" style="width: 100%;" /></a></p>
<p>Earlier this year the company finished taping out both of its lead 18A chips: <a href="https://www.anandtech.com/show/21430/update-on-intel-s-panther-lake-at-computex-2024-intel-powering-up-intel-18a-wafer-next-week">Panther Lake</a> for clients, and <a href="https://www.anandtech.com/show/18797/intel-updates-data-center-roadmap-xeons-on-track-emerald-in-q423-sierra-forest-in-h124">Clearwater Forest</a> for servers. And it’s both chips that are booting. This is made all the more significant by the fact that Clearwater Forest also relies on Intel’s die-to-die hybrid bonding packaging technology, Foveros Direct 3D, where it will be the lead product for that technology as well. Which for Intel, is a promising sign that not only are their silicon lithography ambitions paying off, but their intention to lead in advanced packaging is on-track as well.</p>
<p>And while Intel doesn’t normally talk about yields this early in the game, it’s interesting to note that in a separate Q&A being published this morning with Intel Foundry’s new boss, <a href="https://www.intel.com/content/www/us/en/newsroom/news/kevin-obuckley-talks-progress-intel-18a.html">Kevin O’Buckley</a>, the head of Foundry Services explicitly comments that Panther Lake is “yielding well”. Similarly, Panther Lake’s DDR memory controller (a complex block mixing logic with a PHY) is already running at its target frequency. Progress is going so well, apparently, that according to O’Buckley, it’s ahead of schedule on its product qualification milestones.</p>
<h3>PDK 1.0 Released, First External Customer Tape-Out Expected in H1’25</h3>
<p>As for Intel’s contract foundry business, the company is ramping up its efforts there now that the first full process design kit (PDK) is ready for 18A. Intel released their 18A PDK 1.0 last month, giving Intel’s customers (and potential customers) the tools to finally finish designing their chips for production. As is typically the case of a new node, pre-release PDKs were available for companies to get start... CPUs&body=https://compbuddey.blogspot.com/2024/08/intel-18a-status-update-first-chips_16.html){kind=link}
G.Skill Intros Low Latency DDR5 Memory Modules: CL30 at 6400 MT/s 
G.Skill on Tuesday introduced its ultra-low-latency DDR5-6400 memory modules that feature a CAS latency of 30 clocks, which appears to be the industry's most aggressive timings yet for DDR5-6400 sticks. The modules will be available for both AMD and Intel CPU-based systems.
With every new generation of DDR memory comes an increase in data transfer rates and an extension of relative latencies. While for the vast majority of applications, the increased bandwidth offsets the performance impact of higher timings, there are applications that favor low latencies. However, shrinking latencies is sometimes harder than increasing data transfer rates, which is why low-latency modules are rare.
Nonetheless, G.Skill has apparently managed to cherry-pick enough DDR5 memory chips and build appropriate printed circuit boards to produce DDR5-6400 modules with CL30 timings, which are substantially lower than the CL46 timings recommended by JEDEC for this speed bin. This means that while JEDEC-standard modules have an absolute latency of 14.375 ns, G.Skill's modules can boast a latency of just 9.375 ns – an approximately 35% decrease.
G.Skill's DDR5-6400 CL30 39-39-102 modules have a capacity of 16 GB and will be available in 32 GB dual-channel kits, though the company does not disclose voltages, which are likely considerably higher than those standardized by JEDEC.
The company plans to make its DDR5-6400 modules available both for AMD systems with EXPO profiles (Trident Z5 Neo RGB and Trident Z5 Royal Neo) and for Intel-powered PCs with XMP 3.0 profiles (Trident Z5 RGB and Trident Z5 Royal). For AMD AM5 systems that have a practical limitation of 6000 MT/s – 6400 MT/s for DDR5 memory (as this is roughly as fast as AMD's Infinity Fabric can operate at with a 1:1 ratio), the new modules will be particularly beneficial for AMD's Ryzen 7000 and Ryzen 9000-series processors.
G.Skill notes that since its modules are non-standard, they will not work with all systems but will operate on high-end motherboards with properly cooled CPUs.
The new ultra-low-latency memory kits will be available worldwide from G.Skill's partners starting in late August 2024. The company did not disclose the pricing of these modules, but since we are talking about premium products that boast unique specifications, they are likely to be priced accordingly.
Memory
CXL Gathers Momentum at FMS 2024 
The CXL consortium has had a regular presence at FMS (which rechristened itself from 'Flash Memory Summit' to the 'Future of Memory and Storage' this year). Back at FMS 2022, the company had announced v3.0 of the CXL specifications. This was followed by CXL 3.1's introduction at Supercomputing 2023. Having started off as a host to device interconnect standard, it had slowly subsumed other competing standards such as OpenCAPI and Gen-Z. As a result, the specifications started to encompass a wide variety of use-cases by building a protocol on top of the the ubiquitous PCIe expansion bus. The CXL consortium comprises of heavyweights such as AMD and Intel, as well as a large number of startup companies attempting to play in different segments on the device side. At FMS 2024, CXL had a prime position in the booth demos of many vendors.
The migration of server platforms from DDR4 to DDR5, along with the rise of workloads demanding large RAM capacity (but not particularly sensitive to either memory bandwidth or latency), has opened up memory expansion modules as one of the first set of widely available CXL devices. Over the last couple of years, we have had product announcements from Samsung and Micron in this area.
SK hynix CMM-DDR5 CXL Memory Module and HMSDK
At FMS 2024, SK hynix was showing off their DDR5-based CMM-DDR5 CXL memory module with a 128 GB capacity. The company was also detailing their associated Heterogeneous Memory Software Development Kit (HMSDK) - a set of libraries and tools at both the kernel and user levels aimed at increasing the ease of use of CXL memory. This is achieved in part by considering the memory pyramid / hierarchy and relocating the data between the server's main memory (DRAM) and the CXL device based on usage frequency.
The CMM-DDR5 CXL memory module comes in the SDFF form-factor (E3.S 2T) with a PCIe 3.0 x8 host interface. The internal memory is based on 1α technology DRAM, and the device promises DDR5-class bandwidth and latency within a single NUMA hop. As these memory modules are meant to be used in datacenters and enterprises, the firmware includes features for RAS (reliability, availability, and serviceability) along with secure boot and other management features.
SK hynix was also demonstrating Niagara 2.0 - a hardware solution (currently based on FPGAs) to enable memory pooling and sharing - i.e, connecting multiple CXL memories to allow different hosts (CPUs and GPUs) to optimally share their capacity. The previous version only allowed capacity sharing, but the latest version enables sharing of data also. SK hynix had presented these solutions at the CXL DevCon 2024 earlier this year, but some progress seems to have been made in finalizing the specifications of the CMM-DDR5 at FMS 2024.
Microchip and Micron Demonstrate CZ120 CXL Memory Expansion Module
Micron had unveiled the CZ120 CXL Memory Expansion Module last year based on the Microchip SMC 2000 series CXL memory controller. At FMS 2024, Micron and Microchip had a demonstration of the module on a Granite Rapids server.
Additional insights into the SMC 2000 controller were also provided.
The CXL memory controller also incorporates DRAM die failure handling, and Microchip also provides diagnostics and debug tools to analyze failed modules. The memory controller also supports ECC, which forms part of the enterprise... Storage
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Western Digital Introduces 4 TB microSDUC, 8 TB SDUC, and 16 TB External SSDs
Western Digital's BiCS8 218-layer 3D NAND is being put to good use in a wide range of client and enterprise platforms, including WD's upcoming Gen 5 client SSDs and 128 TB-class datacenter SSD. On the external storage front, the company demonstrated four different products: for card-based media, 4 TB microSDUC and 8 TB SDUC cards with UHS-I speeds, and on the portable SSD front we had two 16 TB drives. One will be a SanDisk Desk Drive with external power, and the other in the SanDisk Extreme Pro housing with a lanyard opening in the case.
All of these are using BiCS8 QLC NAND, though I did hear booth talk (as I was taking leave) that they were not supposed to divulge the use of QLC in these products. The 4 TB microSDUC and 8 TB SDUC cards are rated for UHS-I speeds. They are being marketed under the SanDisk Ultra branding.
The SanDisk Desk Drive is an external SSD with a 18W power adapter, and it has been in the market for a few months now. Initially launched in capacities up to 8 TB, Western Digital had promised a 16 TB version before the end of the year. It appears that the product is coming to retail quite soon. One aspect to note is that this drive has been using TLC for the SKUs that are currently in the market, so it appears unlikely that the 16 TB version would be QLC. The units (at least up to the 8 TB capacity point) come with two SN850XE drives. Given the recent introduction of the 8 TB SN850X, an 'E' version with tweaked firmware is likely to be present in the 16 TB Desk Drive.
The 16 TB portable SSD in the SanDisk Extreme housing was a technology demonstration. It is definitely the highest capacity bus-powered portable SSD demonstrated by any vendor at any trade show thus far. Given the 16 TB Desk Drive's imminent market introduction, it is just a matter of time before the technology demonstration of the bus-powered version becomes a retail reality.
Storage
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