TSMC's Roadmap at a Glance: N3X, N2P, A16 Coming in 2025/2026
As announced last week by TSMC, later this year the company is set to start high-volume manufacturing on its N3P fabrication process, and this will be the company's most advanced node for a while. Next year things will get a bit more interesting as TSMC will have two process technologies that could actually compete against each other when they enter high-volume manufacturing (HVM) in the second half of 2025.
| Advertised PPA Improvements of New Process Technologies Data announced during conference calls, events, press briefings and press releases |
|||||||||
| Compiled by AnandTech |
TSMC | ||||||||
| N3 vs N5 |
N3E vs N5 |
N3P vs N3E |
N3X vs N3P |
N2 vs N3E |
N2P vs N3E |
N2P vs N2 |
A16 vs N2P |
||
| Power | -25% -30% |
-34% | -5% -10% |
-7%*** | -25% -30% |
-30% -40% |
-5% -10% |
-15% -20% |
|
| Performance | +10% +15% |
+18% | +5% | +5% Fmax @1.2V** |
+10% +15% |
+15% +20% |
+5 +10% |
+8% +10% |
|
| Density* | ? | 1.3x | 1.04x | 1.10x*** | 1.15x | 1.15x | ? | 1.07x 1.10x |
|
| HVM | Q4 2022 |
Q4 2023 |
H2 2024 |
H2 2025 |
H2 2025 |
H2 2026 |
H2 2026 |
H2 2026 |
|
*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same area.
***At the same speed.
The production nodes are N3X (3nm-class, extreme performance-focused) as well as N2 (2nm-class). TSMC says that when compared to N3P, chips made on N3X can either lower power consumption by 7% at the same frequency by lowering Vdd from 1.0V to 0.9V, increase performance by 5% at the same area, or increase transistor density by around 10% at the same frequency. Meanwhile, the key advantage of N3X compared to predecessors is its maximum voltage of 1.2V, which is important for ultra-high-performance applications, such as desktop or datacenter GPUs.
TSMC's N2 will be TSMC's first production node to use gate-all-around (GAA) nanosheet transistors and this will significantly enhance its performance, power, and are... Semiconductors
Posted by The Techinical Support
Silicon Motion Demonstrates Flexible Data Placement on MonTitan Gen 5 Enterprise SSD Platform 
At FMS 2024, the technological requirements from the storage and memory subsystem took center stage. Both SSD and controller vendors had various demonstrations touting their suitability for different stages of the AI data pipeline - ingestion, preparation, training, checkpointing, and inference. Vendors like Solidigm have different types of SSDs optimized for different stages of the pipeline. At the same time, controller vendors have taken advantage of one of the features introduced recently in the NVM Express standard - Flexible Data Placement (FDP).
FDP involves the host providing information / hints about the areas where the controller could place the incoming write data in order to reduce the write amplification. These hints are generated based on specific block sizes advertised by the device. The feature is completely backwards-compatible, with non-FDP hosts working just as before with FDP-enabled SSDs, and vice-versa.
Silicon Motion's MonTitan Gen 5 Enterprise SSD Platform was announced back in 2022. Since then, Silicon Motion has been touting the flexibility of the platform, allowing its customers to incorporate their own features as part of the customization process. This approach is common in the enterprise space, as we have seen with Marvell's Bravera SC5 SSD controller in the DapuStor SSDs and Microchip's Flashtec controllers in the Longsys FORESEE enterprise SSDs.
At FMS 2024, the company was demonstrating the advantages of flexible data placement by allowing a single QLC SSD based on their MonTitan platform to take part in different stages of the AI data pipeline while maintaining the required quality of service (minimum bandwidth) for each process. The company even has a trademarked name (PerformaShape) for the firmware feature in the controller that allows the isolation of different concurrent SSD accesses (from different stages in the AI data pipeline) to guarantee this QoS. Silicon Motion claims that this scheme will enable its customers to get the maximum write performance possible from QLC SSDs without negatively impacting the performance of other types of accesses.
Silicon Motion and Phison have market leadership in the client SSD controller market with similar approaches. However, their enterprise SSD controller marketing couldn't be more different. While Phison has gone in for a turnkey solution with their Gen 5 SSD platform (to the extent of not adopting the white label route for this generation, and instead opting to get the SSDs qualified with different cloud service providers themselves), Silicon Motion is opting for a different approach. The flexibility and customization possibilities can make platforms like the MonTitan appeal to flash array vendors.
Storage
U.S. Signs $1.5B in CHIPS Act Agreements With Amkor and SKhynix for Chip Packaging Plants 
Under the CHIPS & Science Act, the U.S. government provided tens of billions of dollars in grants and loans to the world's leading maker of chips, such as Intel, Samsung, and TSMC, which will significantly expand the country's semiconductor production industry in the coming years. However, most chips are typically tested, assembled, and packaged in Asia, which has left the American supply chain incomplete. Addressing this last gap in the government's domestic chip production plans, these past couple of weeks the U.S. government signed memorandums of understanding worth about $1.5 billion with Amkor and SK hynix to support their efforts to build chip packaging facilities in the U.S.
Amkor to Build Advanced Packaging Facility with Apple in Mind
Amkor plans to build a $2 billion advanced packaging facility near Peoria, Arizona, to test and assemble chips produced by TSMC at its Fab 21 near Phoenix, Arizona. The company signed a MOU that offers $400 million in direct funding and access to $200 million in loans under the CHIPS & Science Act. In addition, the company plans to take advantage of a 25% investment tax credit on eligible capital expenditures.
Set to be strategically positioned near TSMC's upcoming Fab 21 complex in Arizona, Amkor's Peoria facility will occupy 55 acres and, when fully completed, will feature over 500,000 square feet (46,451 square meters) of cleanroom space, more than twice the size of Amkor's advanced packaging site in Vietnam. Although the company has not disclosed the exact capacity or the specific technologies the facility will support, it is expected to cater to a wide range of industries, including automotive, high-performance computing, and mobile technologies. This suggests the new plant will offer diverse packaging solutions, including traditional, 2.5D, and 3D technologies.
Amkor has collaborated extensively with Apple on the vision and initial setup of the Peoria facility, as Apple is slated to be the facility's first and largest customer, marking a significant commitment from the tech giant. This partnership highlights the importance of the new facility in reinforcing the U.S. semiconductor supply chain and positioning Amkor as a key partner for companies relying on TSMC's manufacturing capabilities. The project is expected to generate around 2,000 jobs and is scheduled to begin operations in 2027.
SK hynix to Build HBM4 in the U.S.
This week SK hynix also signed a preliminary agreement with the U.S. government to receive up to $450 million in direct funding and $500 million in loans to build an advanced memory packaging facility in West Lafayette, Indiana.
The proposed facility is scheduled to begin operations in 2028, which means that it will assemble HBM4 or HBM4E memory. Meanwhile, DRAM devices for high bandwidth memory (HBM) stacks will still be produced in South Korea. Nonetheless, packing finished HBM4/HBM4E in the U.S. and possibly integrating these memory modules with high-end processors is a big deal.
In addition to building its packaging plant, SK hynix plans to collaborate with Purdue University and other local research institutions to advance semiconductor technology and packaging innovations. This partnership is intended to bolster research and development in the region, positioning the facility as a hub for AI technology and skilled employment.
Semiconductors
Fadu's FC5161 SSD Controller Breaks Cover in Western Digital's PCIe Gen5 Enterprise Drives 
When Western Digital introduced its Ultrastar DC SN861 SSDs earlier this year, the company did not disclose which controller it used for these drives, which made many observers presume that WD was using an in-house controller. But a recent teardown of the drive shows that is not the case; instead, the company is using a controller from Fadu, a South Korean company founded in 2015 that specializes on enterprise-grade turnkey SSD solutions.
The Western Digital Ultrastar DC SN861 SSD is aimed at performance-hungry hyperscale datacenters and enterprise customers which are adopting PCIe Gen5 storage devices these days. And, as uncovered in photos from a recent Storage Review article, the drive is based on Fadu's FC5161 NVMe 2.0-compliant controller. The FC5161 utilizes 16 NAND channels supporting an ONFi 5.0 2400 MT/s interface, and features a combination of enterprise-grade capabilities (OCP Cloud Spec 2.0, SR-IOV, up to 512 name spaces for ZNS support, flexible data placement, NVMe-MI 1.2, advanced security, telemetry, power loss protection) not available on other off-the-shelf controllers – or on any previous Western Digital controllers.
The Ultrastar DC SN861 SSD offers sequential read speeds up to 13.7 GB/s as well as sequential write speeds up to 7.5 GB/s. As for random performance, it boasts with an up to 3.3 million random 4K read IOPS and up to 0.8 million random 4K write IOPS. The drives are available in capacities between 1.6 TB and 7.68 TB with one or three drive writes per day (DWPD) over five years rating as well as in U.2 and E1.S form-factors.
While the two form factors of the SN861 share a similar technical design, Western Digital has tailored each version for distinct workloads: the E1.S supports FDP and performance enhancements specifically for cloud environments. By contrast, the U.2 model is geared towards high-performance enterprise tasks and emerging applications like AI.
Without any doubts, Western Digital's Ultrastar DC SN861 is a feature-rich high-performance enterprise-grade SSD. It has another distinctive feature: a 5W idle power consumption, which is rather low by the standards of enterprise-grade drives (e.g., it is 1W lower compared to the SN840). While the difference with predecessors may be just 1W, hyperscalers deploy thousands of drives and for their TCO every watt counts.
Western Digital's Ultrastar DC SN861 SSDs are now available for purchase to select customers (such as Meta) and to interested parties. Prices are unknown, but they will depend on such factors as volumes.
Sources: Fadu, Storage Review
Storage
Silicon Motion Demonstrates Flexible Data Placement on MonTitan Gen 5 Enterprise SSD Platform
At FMS 2024, the technological requirements from the storage and memory subsystem took center stage. Both SSD and controller vendors had various demonstrations touting their suitability for different stages of the AI data pipeline - ingestion, preparation, training, checkpointing, and inference. Vendors like Solidigm have different types of SSDs optimized for different stages of the pipeline. At the same time, controller vendors have taken advantage of one of the features introduced recently in the NVM Express standard - Flexible Data Placement (FDP).
FDP involves the host providing information / hints about the areas where the controller could place the incoming write data in order to reduce the write amplification. These hints are generated based on specific block sizes advertised by the device. The feature is completely backwards-compatible, with non-FDP hosts working just as before with FDP-enabled SSDs, and vice-versa.
Silicon Motion's MonTitan Gen 5 Enterprise SSD Platform was announced back in 2022. Since then, Silicon Motion has been touting the flexibility of the platform, allowing its customers to incorporate their own features as part of the customization process. This approach is common in the enterprise space, as we have seen with Marvell's Bravera SC5 SSD controller in the DapuStor SSDs and Microchip's Flashtec controllers in the Longsys FORESEE enterprise SSDs.
At FMS 2024, the company was demonstrating the advantages of flexible data placement by allowing a single QLC SSD based on their MonTitan platform to take part in different stages of the AI data pipeline while maintaining the required quality of service (minimum bandwidth) for each process. The company even has a trademarked name (PerformaShape) for the firmware feature in the controller that allows the isolation of different concurrent SSD accesses (from different stages in the AI data pipeline) to guarantee this QoS. Silicon Motion claims that this scheme will enable its customers to get the maximum write performance possible from QLC SSDs without negatively impacting the performance of other types of accesses.
Silicon Motion and Phison have market leadership in the client SSD controller market with similar approaches. However, their enterprise SSD controller marketing couldn't be more different. While Phison has gone in for a turnkey solution with their Gen 5 SSD platform (to the extent of not adopting the white label route for this generation, and instead opting to get the SSDs qualified with different cloud service providers themselves), Silicon Motion is opting for a different approach. The flexibility and customization possibilities can make platforms like the MonTitan appeal to flash array vendors.
Storage
U.S. Signs $1.5B in CHIPS Act Agreements With Amkor and SKhynix for Chip Packaging Plants
Under the CHIPS & Science Act, the U.S. government provided tens of billions of dollars in grants and loans to the world's leading maker of chips, such as Intel, Samsung, and TSMC, which will significantly expand the country's semiconductor production industry in the coming years. However, most chips are typically tested, assembled, and packaged in Asia, which has left the American supply chain incomplete. Addressing this last gap in the government's domestic chip production plans, these past couple of weeks the U.S. government signed memorandums of understanding worth about $1.5 billion with Amkor and SK hynix to support their efforts to build chip packaging facilities in the U.S.
Amkor to Build Advanced Packaging Facility with Apple in Mind
Amkor plans to build a $2 billion advanced packaging facility near Peoria, Arizona, to test and assemble chips produced by TSMC at its Fab 21 near Phoenix, Arizona. The company signed a MOU that offers $400 million in direct funding and access to $200 million in loans under the CHIPS & Science Act. In addition, the company plans to take advantage of a 25% investment tax credit on eligible capital expenditures.
Set to be strategically positioned near TSMC's upcoming Fab 21 complex in Arizona, Amkor's Peoria facility will occupy 55 acres and, when fully completed, will feature over 500,000 square feet (46,451 square meters) of cleanroom space, more than twice the size of Amkor's advanced packaging site in Vietnam. Although the company has not disclosed the exact capacity or the specific technologies the facility will support, it is expected to cater to a wide range of industries, including automotive, high-performance computing, and mobile technologies. This suggests the new plant will offer diverse packaging solutions, including traditional, 2.5D, and 3D technologies.
Amkor has collaborated extensively with Apple on the vision and initial setup of the Peoria facility, as Apple is slated to be the facility's first and largest customer, marking a significant commitment from the tech giant. This partnership highlights the importance of the new facility in reinforcing the U.S. semiconductor supply chain and positioning Amkor as a key partner for companies relying on TSMC's manufacturing capabilities. The project is expected to generate around 2,000 jobs and is scheduled to begin operations in 2027.
SK hynix to Build HBM4 in the U.S.
This week SK hynix also signed a preliminary agreement with the U.S. government to receive up to $450 million in direct funding and $500 million in loans to build an advanced memory packaging facility in West Lafayette, Indiana.
The proposed facility is scheduled to begin operations in 2028, which means that it will assemble HBM4 or HBM4E memory. Meanwhile, DRAM devices for high bandwidth memory (HBM) stacks will still be produced in South Korea. Nonetheless, packing finished HBM4/HBM4E in the U.S. and possibly integrating these memory modules with high-end processors is a big deal.
In addition to building its packaging plant, SK hynix plans to collaborate with Purdue University and other local research institutions to advance semiconductor technology and packaging innovations. This partnership is intended to bolster research and development in the region, positioning the facility as a hub for AI technology and skilled employment.
Semiconductors
Fadu's FC5161 SSD Controller Breaks Cover in Western Digital's PCIe Gen5 Enterprise Drives
When Western Digital introduced its Ultrastar DC SN861 SSDs earlier this year, the company did not disclose which controller it used for these drives, which made many observers presume that WD was using an in-house controller. But a recent teardown of the drive shows that is not the case; instead, the company is using a controller from Fadu, a South Korean company founded in 2015 that specializes on enterprise-grade turnkey SSD solutions.
The Western Digital Ultrastar DC SN861 SSD is aimed at performance-hungry hyperscale datacenters and enterprise customers which are adopting PCIe Gen5 storage devices these days. And, as uncovered in photos from a recent Storage Review article, the drive is based on Fadu's FC5161 NVMe 2.0-compliant controller. The FC5161 utilizes 16 NAND channels supporting an ONFi 5.0 2400 MT/s interface, and features a combination of enterprise-grade capabilities (OCP Cloud Spec 2.0, SR-IOV, up to 512 name spaces for ZNS support, flexible data placement, NVMe-MI 1.2, advanced security, telemetry, power loss protection) not available on other off-the-shelf controllers – or on any previous Western Digital controllers.
The Ultrastar DC SN861 SSD offers sequential read speeds up to 13.7 GB/s as well as sequential write speeds up to 7.5 GB/s. As for random performance, it boasts with an up to 3.3 million random 4K read IOPS and up to 0.8 million random 4K write IOPS. The drives are available in capacities between 1.6 TB and 7.68 TB with one or three drive writes per day (DWPD) over five years rating as well as in U.2 and E1.S form-factors.
While the two form factors of the SN861 share a similar technical design, Western Digital has tailored each version for distinct workloads: the E1.S supports FDP and performance enhancements specifically for cloud environments. By contrast, the U.2 model is geared towards high-performance enterprise tasks and emerging applications like AI.
Without any doubts, Western Digital's Ultrastar DC SN861 is a feature-rich high-performance enterprise-grade SSD. It has another distinctive feature: a 5W idle power consumption, which is rather low by the standards of enterprise-grade drives (e.g., it is 1W lower compared to the SN840). While the difference with predecessors may be just 1W, hyperscalers deploy thousands of drives and for their TCO every watt counts.
Western Digital's Ultrastar DC SN861 SSDs are now available for purchase to select customers (such as Meta) and to interested parties. Prices are unknown, but they will depend on such factors as volumes.
Sources: Fadu, Storage Review
Storage
CXL Gathers Momentum at FMS 2024 
The CXL consortium has had a regular presence at FMS (which rechristened itself from 'Flash Memory Summit' to the 'Future of Memory and Storage' this year). Back at FMS 2022, the company had announced v3.0 of the CXL specifications. This was followed by CXL 3.1's introduction at Supercomputing 2023. Having started off as a host to device interconnect standard, it had slowly subsumed other competing standards such as OpenCAPI and Gen-Z. As a result, the specifications started to encompass a wide variety of use-cases by building a protocol on top of the the ubiquitous PCIe expansion bus. The CXL consortium comprises of heavyweights such as AMD and Intel, as well as a large number of startup companies attempting to play in different segments on the device side. At FMS 2024, CXL had a prime position in the booth demos of many vendors.
The migration of server platforms from DDR4 to DDR5, along with the rise of workloads demanding large RAM capacity (but not particularly sensitive to either memory bandwidth or latency), has opened up memory expansion modules as one of the first set of widely available CXL devices. Over the last couple of years, we have had product announcements from Samsung and Micron in this area.
SK hynix CMM-DDR5 CXL Memory Module and HMSDK
At FMS 2024, SK hynix was showing off their DDR5-based CMM-DDR5 CXL memory module with a 128 GB capacity. The company was also detailing their associated Heterogeneous Memory Software Development Kit (HMSDK) - a set of libraries and tools at both the kernel and user levels aimed at increasing the ease of use of CXL memory. This is achieved in part by considering the memory pyramid / hierarchy and relocating the data between the server's main memory (DRAM) and the CXL device based on usage frequency.
The CMM-DDR5 CXL memory module comes in the SDFF form-factor (E3.S 2T) with a PCIe 3.0 x8 host interface. The internal memory is based on 1α technology DRAM, and the device promises DDR5-class bandwidth and latency within a single NUMA hop. As these memory modules are meant to be used in datacenters and enterprises, the firmware includes features for RAS (reliability, availability, and serviceability) along with secure boot and other management features.
SK hynix was also demonstrating Niagara 2.0 - a hardware solution (currently based on FPGAs) to enable memory pooling and sharing - i.e, connecting multiple CXL memories to allow different hosts (CPUs and GPUs) to optimally share their capacity. The previous version only allowed capacity sharing, but the latest version enables sharing of data also. SK hynix had presented these solutions at the CXL DevCon 2024 earlier this year, but some progress seems to have been made in finalizing the specifications of the CMM-DDR5 at FMS 2024.
Microchip and Micron Demonstrate CZ120 CXL Memory Expansion Module
Micron had unveiled the CZ120 CXL Memory Expansion Module last year based on the Microchip SMC 2000 series CXL memory controller. At FMS 2024, Micron and Microchip had a demonstration of the module on a Granite Rapids server.
Additional insights into the SMC 2000 controller were also provided.
The CXL memory controller also incorporates DRAM die failure handling, and Microchip also provides diagnostics and debug tools to analyze failed modules. The memory controller also supports ECC, which forms part of the enterprise... Storage
The Endorfy Fortis 5 Dual Fan CPU Cooler Review: Towering Value Standard CPU coolers, while adequate for managing basic thermal loads, often fall short in terms of noise reduction and superior cooling efficiency. This limitation drives advanced users and system builders to seek aftermarket solutions tailored to their specific needs. The high-end aftermarket cooler market is highly competitive, with manufacturers striving to offer products with exceptional performance.
Endorfy, previously known as SilentiumPC, is a Polish manufacturer that has undergone a significant transformation to expand its presence in global markets. The brand is known for delivering high-performance cooling solutions with a strong focus on balancing efficiency and affordability. By rebranding as Endorfy, the company aims to enter premium market segments while continuing to offer reliable, high-quality cooling products.
SilentiumPC became very popular in the value/mainstream segments of the PC market with their products, the spearhead of which probably was the Fera 5 cooler that we reviewed a little over two years ago and had a remarkable value for money. Today’s review places Endorfy’s largest CPU cooler, the Fortis 5 Dual Fan, on our laboratory test bench. The Fortis 5 is the largest CPU air cooler the company currently offers and is significantly more expensive than the Fera 5, yet it still is a single-tower cooler that strives to strike a balance between value, compatibility, and performance.
Cases/Cooling/PSUs
Fadu's FC5161 SSD Controller Breaks Cover in Western Digital's PCIe Gen5 Enterprise Drives
When Western Digital introduced its Ultrastar DC SN861 SSDs earlier this year, the company did not disclose which controller it used for these drives, which made many observers presume that WD was using an in-house controller. But a recent teardown of the drive shows that is not the case; instead, the company is using a controller from Fadu, a South Korean company founded in 2015 that specializes on enterprise-grade turnkey SSD solutions.
The Western Digital Ultrastar DC SN861 SSD is aimed at performance-hungry hyperscale datacenters and enterprise customers which are adopting PCIe Gen5 storage devices these days. And, as uncovered in photos from a recent Storage Review article, the drive is based on Fadu's FC5161 NVMe 2.0-compliant controller. The FC5161 utilizes 16 NAND channels supporting an ONFi 5.0 2400 MT/s interface, and features a combination of enterprise-grade capabilities (OCP Cloud Spec 2.0, SR-IOV, up to 512 name spaces for ZNS support, flexible data placement, NVMe-MI 1.2, advanced security, telemetry, power loss protection) not available on other off-the-shelf controllers – or on any previous Western Digital controllers.
The Ultrastar DC SN861 SSD offers sequential read speeds up to 13.7 GB/s as well as sequential write speeds up to 7.5 GB/s. As for random performance, it boasts with an up to 3.3 million random 4K read IOPS and up to 0.8 million random 4K write IOPS. The drives are available in capacities between 1.6 TB and 7.68 TB with one or three drive writes per day (DWPD) over five years rating as well as in U.2 and E1.S form-factors.
While the two form factors of the SN861 share a similar technical design, Western Digital has tailored each version for distinct workloads: the E1.S supports FDP and performance enhancements specifically for cloud environments. By contrast, the U.2 model is geared towards high-performance enterprise tasks and emerging applications like AI.
Without any doubts, Western Digital's Ultrastar DC SN861 is a feature-rich high-performance enterprise-grade SSD. It has another distinctive feature: a 5W idle power consumption, which is rather low by the standards of enterprise-grade drives (e.g., it is 1W lower compared to the SN840). While the difference with predecessors may be just 1W, hyperscalers deploy thousands of drives and for their TCO every watt counts.
Western Digital's Ultrastar DC SN861 SSDs are now available for purchase to select customers (such as Meta) and to interested parties. Prices are unknown, but they will depend on such factors as volumes.
Sources: Fadu, Storage Review
Storage
![](https://twitter.com/share?url=https://compbuddey.blogspot.com/2024/05/tsmcs-roadmap-at-glance-n3x-n2p-a16_29.html&text=TSMC's Roadmap at a Glance: N3X, N2P, A16 Coming in 2025/2026 <p align="center"><a href="https://www.anandtech.com/show/21408/tsmc-roadmap-at-a-glance-n3x-n2p-a16-2025-2026"><img src="https://images.anandtech.com/doci/21408/tsmc-wafer-semiconductor-chip-fab-678_575px.jpg" alt="" /></a></p><p><p>As announced last week by TSMC, later this year the company is set to start high-volume manufacturing on its N3P fabrication process, and this will be the company's most advanced node for a while. Next year things will get a bit more interesting as TSMC will have two process technologies that could actually compete against each other when they enter high-volume manufacturing (HVM) in the second half of 2025.</p>
<table align="center" border="0" cellpadding="0" cellspacing="1" style="background-color: rgb(246, 246, 246);" width="680">
<tbody>
<tr class="tgrey">
<td align="center" colspan="10">Advertised PPA Improvements of New Process Technologies<br />
<small>Data announced during conference calls, events, press briefings and press releases</small></td>
</tr>
<tr class="tlblue">
<td rowspan="2" width="186">Compiled<br />
by<br />
AnandTech</td>
<td align="center" colspan="8" width="137">TSMC</td>
</tr>
<tr class="tlblue">
<td align="center" valign="middle" width="136">N3<br />
vs<br />
N5</td>
<td align="center" valign="middle" width="136">N3E<br />
vs<br />
N5</td>
<td align="center" valign="middle" width="136">N3P<br />
vs<br />
N3E</td>
<td align="center" valign="middle" width="136">N3X<br />
vs<br />
N3P</td>
<td align="center" valign="middle" width="136">N2<br />
vs<br />
N3E</td>
<td align="center" valign="middle" width="136">N2P<br />
vs<br />
N3E</td>
<td align="center" valign="middle" width="136">N2P<br />
vs<br />
N2</td>
<td align="center" valign="middle" width="136">A16<br />
vs<br />
N2P</td>
</tr>
<tr>
<td class="tlgrey">Power</td>
<td align="center" valign="middle">-25%<br />
-30%</td>
<td align="center" valign="middle">-34%</td>
<td align="center" valign="middle">-5%<br />
-10%</td>
<td align="center" valign="middle">-7%***</td>
<td align="center" valign="middle"><span style="caret-color: rgb(68, 68, 68); color: rgb(68, 68, 68); text-align: -webkit-center; background-color: rgb(238, 238, 238);">-25%<br />
-30%</span></td>
<td align="center" valign="middle">-30%<br />
-40%</td>
<td align="center" valign="middle">-5%<br />
-10%</td>
<td align="center" valign="middle">-15%<br />
-20%</td>
</tr>
<tr>
<td class="tlgrey">Performance</td>
<td align="center" valign="middle">+10%<br />
+15%</td>
<td align="center" valign="middle">+18%</td>
<td align="center" valign="middle">+5%</td>
<td align="center" valign="middle">+5%<br />
Fmax @1.2V**</td>
<td align="center" valign="middle">+10%<br />
+15%</td>
<td align="center" valign="middle">+15%<br />
+20%</td>
<td align="center" valign="middle">+5<br />
+10%</td>
<td align="center" valign="middle">+8%<br />
+10%</td>
</tr>
<tr>
<td class="tlgrey">Density*</td>
<td align="center" valign="middle">?</td>
<td align="center" valign="middle">1.3x</td>
<td align="center" valign="middle">1.04x</td>
<td align="center" valign="middle">1.10x***</td>
<td align="center" valign="middle">1.15x</td>
<td align="center" valign="middle">1.15x</td>
<td align="center" valign="middle">?</td>
<td align="center" valign="middle">1.07x<br />
1.10x</td>
</tr>
<tr>
<td class="tlgrey">HVM</td>
<td align="center" valign="middle">Q4<br />
2022</td>
<td align="center" valign="middle">Q4<br />
2023</td>
<td align="center" valign="middle">H2<br />
2024</td>
<td align="center" valign="middle">H2<br />
2025</td>
<td align="center" valign="middle">H2<br />
2025</td>
<td align="center" valign="middle">H2<br />
2026</td>
<td align="center" valign="middle">H2<br />
2026</td>
<td align="center" valign="middle">H2<br />
2026</td>
</tr>
</tbody>
</table>
<p><small>*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.<br />
**At the same area. <br />
***At the same speed.</small></p>
<p>The production nodes are N3X (3nm-class, extreme performance-focused) as well as N2 (2nm-class). TSMC says that when compared to N3P, chips made on N3X can either lower power consumption by 7% at the same frequency by lowering Vdd from 1.0V to 0.9V, increase performance by 5% at the same area, or increase transistor density by around 10% at the same frequency. Meanwhile, the key advantage of N3X compared to predecessors is its maximum voltage of 1.2V, which is important for ultra-high-performance applications, such as desktop or datacenter GPUs.</p>
<p>TSMC's N2 will be TSMC's first production node to use gate-all-around (GAA) nanosheet transistors and this will significantly enhance its performance, power, and are... Semiconductors){kind=link}
![](https://www.pinterest.com/pin/create/button/?url=https://compbuddey.blogspot.com/2024/05/tsmcs-roadmap-at-glance-n3x-n2p-a16_29.html&media=https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tqGQq3TLkTctxJ1P0ylpR-gBrsTSI21aA3_jTtA8d2d3ayyfBwg14X7Z6pccyx_ds_uSzgIrOMHI6wRw3wb7Ya7ZXjHxDYxbSMBHWM8XXEhgiug7lImD3WfGqQQoDvjGPro8EEPEovIeeY3gOvAhREnfy29ccxrDJxZw&description=TSMC's Roadmap at a Glance: N3X, N2P, A16 Coming in 2025/2026 <p align="center"><a href="https://www.anandtech.com/show/21408/tsmc-roadmap-at-a-glance-n3x-n2p-a16-2025-2026"><img src="https://images.anandtech.com/doci/21408/tsmc-wafer-semiconductor-chip-fab-678_575px.jpg" alt="" /></a></p><p><p>As announced last week by TSMC, later this year the company is set to start high-volume manufacturing on its N3P fabrication process, and this will be the company's most advanced node for a while. Next year things will get a bit more interesting as TSMC will have two process technologies that could actually compete against each other when they enter high-volume manufacturing (HVM) in the second half of 2025.</p>
<table align="center" border="0" cellpadding="0" cellspacing="1" style="background-color: rgb(246, 246, 246);" width="680">
<tbody>
<tr class="tgrey">
<td align="center" colspan="10">Advertised PPA Improvements of New Process Technologies<br />
<small>Data announced during conference calls, events, press briefings and press releases</small></td>
</tr>
<tr class="tlblue">
<td rowspan="2" width="186">Compiled<br />
by<br />
AnandTech</td>
<td align="center" colspan="8" width="137">TSMC</td>
</tr>
<tr class="tlblue">
<td align="center" valign="middle" width="136">N3<br />
vs<br />
N5</td>
<td align="center" valign="middle" width="136">N3E<br />
vs<br />
N5</td>
<td align="center" valign="middle" width="136">N3P<br />
vs<br />
N3E</td>
<td align="center" valign="middle" width="136">N3X<br />
vs<br />
N3P</td>
<td align="center" valign="middle" width="136">N2<br />
vs<br />
N3E</td>
<td align="center" valign="middle" width="136">N2P<br />
vs<br />
N3E</td>
<td align="center" valign="middle" width="136">N2P<br />
vs<br />
N2</td>
<td align="center" valign="middle" width="136">A16<br />
vs<br />
N2P</td>
</tr>
<tr>
<td class="tlgrey">Power</td>
<td align="center" valign="middle">-25%<br />
-30%</td>
<td align="center" valign="middle">-34%</td>
<td align="center" valign="middle">-5%<br />
-10%</td>
<td align="center" valign="middle">-7%***</td>
<td align="center" valign="middle"><span style="caret-color: rgb(68, 68, 68); color: rgb(68, 68, 68); text-align: -webkit-center; background-color: rgb(238, 238, 238);">-25%<br />
-30%</span></td>
<td align="center" valign="middle">-30%<br />
-40%</td>
<td align="center" valign="middle">-5%<br />
-10%</td>
<td align="center" valign="middle">-15%<br />
-20%</td>
</tr>
<tr>
<td class="tlgrey">Performance</td>
<td align="center" valign="middle">+10%<br />
+15%</td>
<td align="center" valign="middle">+18%</td>
<td align="center" valign="middle">+5%</td>
<td align="center" valign="middle">+5%<br />
Fmax @1.2V**</td>
<td align="center" valign="middle">+10%<br />
+15%</td>
<td align="center" valign="middle">+15%<br />
+20%</td>
<td align="center" valign="middle">+5<br />
+10%</td>
<td align="center" valign="middle">+8%<br />
+10%</td>
</tr>
<tr>
<td class="tlgrey">Density*</td>
<td align="center" valign="middle">?</td>
<td align="center" valign="middle">1.3x</td>
<td align="center" valign="middle">1.04x</td>
<td align="center" valign="middle">1.10x***</td>
<td align="center" valign="middle">1.15x</td>
<td align="center" valign="middle">1.15x</td>
<td align="center" valign="middle">?</td>
<td align="center" valign="middle">1.07x<br />
1.10x</td>
</tr>
<tr>
<td class="tlgrey">HVM</td>
<td align="center" valign="middle">Q4<br />
2022</td>
<td align="center" valign="middle">Q4<br />
2023</td>
<td align="center" valign="middle">H2<br />
2024</td>
<td align="center" valign="middle">H2<br />
2025</td>
<td align="center" valign="middle">H2<br />
2025</td>
<td align="center" valign="middle">H2<br />
2026</td>
<td align="center" valign="middle">H2<br />
2026</td>
<td align="center" valign="middle">H2<br />
2026</td>
</tr>
</tbody>
</table>
<p><small>*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.<br />
**At the same area. <br />
***At the same speed.</small></p>
<p>The production nodes are N3X (3nm-class, extreme performance-focused) as well as N2 (2nm-class). TSMC says that when compared to N3P, chips made on N3X can either lower power consumption by 7% at the same frequency by lowering Vdd from 1.0V to 0.9V, increase performance by 5% at the same area, or increase transistor density by around 10% at the same frequency. Meanwhile, the key advantage of N3X compared to predecessors is its maximum voltage of 1.2V, which is important for ultra-high-performance applications, such as desktop or datacenter GPUs.</p>
<p>TSMC's N2 will be TSMC's first production node to use gate-all-around (GAA) nanosheet transistors and this will significantly enhance its performance, power, and are... Semiconductors){kind=link}
![](https://web.whatsapp.com/send?text=TSMC's Roadmap at a Glance: N3X, N2P, A16 Coming in 2025/2026 <p align="center"><a href="https://www.anandtech.com/show/21408/tsmc-roadmap-at-a-glance-n3x-n2p-a16-2025-2026"><img src="https://images.anandtech.com/doci/21408/tsmc-wafer-semiconductor-chip-fab-678_575px.jpg" alt="" /></a></p><p><p>As announced last week by TSMC, later this year the company is set to start high-volume manufacturing on its N3P fabrication process, and this will be the company's most advanced node for a while. Next year things will get a bit more interesting as TSMC will have two process technologies that could actually compete against each other when they enter high-volume manufacturing (HVM) in the second half of 2025.</p>
<table align="center" border="0" cellpadding="0" cellspacing="1" style="background-color: rgb(246, 246, 246);" width="680">
<tbody>
<tr class="tgrey">
<td align="center" colspan="10">Advertised PPA Improvements of New Process Technologies<br />
<small>Data announced during conference calls, events, press briefings and press releases</small></td>
</tr>
<tr class="tlblue">
<td rowspan="2" width="186">Compiled<br />
by<br />
AnandTech</td>
<td align="center" colspan="8" width="137">TSMC</td>
</tr>
<tr class="tlblue">
<td align="center" valign="middle" width="136">N3<br />
vs<br />
N5</td>
<td align="center" valign="middle" width="136">N3E<br />
vs<br />
N5</td>
<td align="center" valign="middle" width="136">N3P<br />
vs<br />
N3E</td>
<td align="center" valign="middle" width="136">N3X<br />
vs<br />
N3P</td>
<td align="center" valign="middle" width="136">N2<br />
vs<br />
N3E</td>
<td align="center" valign="middle" width="136">N2P<br />
vs<br />
N3E</td>
<td align="center" valign="middle" width="136">N2P<br />
vs<br />
N2</td>
<td align="center" valign="middle" width="136">A16<br />
vs<br />
N2P</td>
</tr>
<tr>
<td class="tlgrey">Power</td>
<td align="center" valign="middle">-25%<br />
-30%</td>
<td align="center" valign="middle">-34%</td>
<td align="center" valign="middle">-5%<br />
-10%</td>
<td align="center" valign="middle">-7%***</td>
<td align="center" valign="middle"><span style="caret-color: rgb(68, 68, 68); color: rgb(68, 68, 68); text-align: -webkit-center; background-color: rgb(238, 238, 238);">-25%<br />
-30%</span></td>
<td align="center" valign="middle">-30%<br />
-40%</td>
<td align="center" valign="middle">-5%<br />
-10%</td>
<td align="center" valign="middle">-15%<br />
-20%</td>
</tr>
<tr>
<td class="tlgrey">Performance</td>
<td align="center" valign="middle">+10%<br />
+15%</td>
<td align="center" valign="middle">+18%</td>
<td align="center" valign="middle">+5%</td>
<td align="center" valign="middle">+5%<br />
Fmax @1.2V**</td>
<td align="center" valign="middle">+10%<br />
+15%</td>
<td align="center" valign="middle">+15%<br />
+20%</td>
<td align="center" valign="middle">+5<br />
+10%</td>
<td align="center" valign="middle">+8%<br />
+10%</td>
</tr>
<tr>
<td class="tlgrey">Density*</td>
<td align="center" valign="middle">?</td>
<td align="center" valign="middle">1.3x</td>
<td align="center" valign="middle">1.04x</td>
<td align="center" valign="middle">1.10x***</td>
<td align="center" valign="middle">1.15x</td>
<td align="center" valign="middle">1.15x</td>
<td align="center" valign="middle">?</td>
<td align="center" valign="middle">1.07x<br />
1.10x</td>
</tr>
<tr>
<td class="tlgrey">HVM</td>
<td align="center" valign="middle">Q4<br />
2022</td>
<td align="center" valign="middle">Q4<br />
2023</td>
<td align="center" valign="middle">H2<br />
2024</td>
<td align="center" valign="middle">H2<br />
2025</td>
<td align="center" valign="middle">H2<br />
2025</td>
<td align="center" valign="middle">H2<br />
2026</td>
<td align="center" valign="middle">H2<br />
2026</td>
<td align="center" valign="middle">H2<br />
2026</td>
</tr>
</tbody>
</table>
<p><small>*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.<br />
**At the same area. <br />
***At the same speed.</small></p>
<p>The production nodes are N3X (3nm-class, extreme performance-focused) as well as N2 (2nm-class). TSMC says that when compared to N3P, chips made on N3X can either lower power consumption by 7% at the same frequency by lowering Vdd from 1.0V to 0.9V, increase performance by 5% at the same area, or increase transistor density by around 10% at the same frequency. Meanwhile, the key advantage of N3X compared to predecessors is its maximum voltage of 1.2V, which is important for ultra-high-performance applications, such as desktop or datacenter GPUs.</p>
<p>TSMC's N2 will be TSMC's first production node to use gate-all-around (GAA) nanosheet transistors and this will significantly enhance its performance, power, and are... Semiconductors | https://compbuddey.blogspot.com/2024/05/tsmcs-roadmap-at-glance-n3x-n2p-a16_29.html){kind=link}
![](mailto:?subject=TSMC's Roadmap at a Glance: N3X, N2P, A16 Coming in 2025/2026 <p align="center"><a href="https://www.anandtech.com/show/21408/tsmc-roadmap-at-a-glance-n3x-n2p-a16-2025-2026"><img src="https://images.anandtech.com/doci/21408/tsmc-wafer-semiconductor-chip-fab-678_575px.jpg" alt="" /></a></p><p><p>As announced last week by TSMC, later this year the company is set to start high-volume manufacturing on its N3P fabrication process, and this will be the company's most advanced node for a while. Next year things will get a bit more interesting as TSMC will have two process technologies that could actually compete against each other when they enter high-volume manufacturing (HVM) in the second half of 2025.</p>
<table align="center" border="0" cellpadding="0" cellspacing="1" style="background-color: rgb(246, 246, 246);" width="680">
<tbody>
<tr class="tgrey">
<td align="center" colspan="10">Advertised PPA Improvements of New Process Technologies<br />
<small>Data announced during conference calls, events, press briefings and press releases</small></td>
</tr>
<tr class="tlblue">
<td rowspan="2" width="186">Compiled<br />
by<br />
AnandTech</td>
<td align="center" colspan="8" width="137">TSMC</td>
</tr>
<tr class="tlblue">
<td align="center" valign="middle" width="136">N3<br />
vs<br />
N5</td>
<td align="center" valign="middle" width="136">N3E<br />
vs<br />
N5</td>
<td align="center" valign="middle" width="136">N3P<br />
vs<br />
N3E</td>
<td align="center" valign="middle" width="136">N3X<br />
vs<br />
N3P</td>
<td align="center" valign="middle" width="136">N2<br />
vs<br />
N3E</td>
<td align="center" valign="middle" width="136">N2P<br />
vs<br />
N3E</td>
<td align="center" valign="middle" width="136">N2P<br />
vs<br />
N2</td>
<td align="center" valign="middle" width="136">A16<br />
vs<br />
N2P</td>
</tr>
<tr>
<td class="tlgrey">Power</td>
<td align="center" valign="middle">-25%<br />
-30%</td>
<td align="center" valign="middle">-34%</td>
<td align="center" valign="middle">-5%<br />
-10%</td>
<td align="center" valign="middle">-7%***</td>
<td align="center" valign="middle"><span style="caret-color: rgb(68, 68, 68); color: rgb(68, 68, 68); text-align: -webkit-center; background-color: rgb(238, 238, 238);">-25%<br />
-30%</span></td>
<td align="center" valign="middle">-30%<br />
-40%</td>
<td align="center" valign="middle">-5%<br />
-10%</td>
<td align="center" valign="middle">-15%<br />
-20%</td>
</tr>
<tr>
<td class="tlgrey">Performance</td>
<td align="center" valign="middle">+10%<br />
+15%</td>
<td align="center" valign="middle">+18%</td>
<td align="center" valign="middle">+5%</td>
<td align="center" valign="middle">+5%<br />
Fmax @1.2V**</td>
<td align="center" valign="middle">+10%<br />
+15%</td>
<td align="center" valign="middle">+15%<br />
+20%</td>
<td align="center" valign="middle">+5<br />
+10%</td>
<td align="center" valign="middle">+8%<br />
+10%</td>
</tr>
<tr>
<td class="tlgrey">Density*</td>
<td align="center" valign="middle">?</td>
<td align="center" valign="middle">1.3x</td>
<td align="center" valign="middle">1.04x</td>
<td align="center" valign="middle">1.10x***</td>
<td align="center" valign="middle">1.15x</td>
<td align="center" valign="middle">1.15x</td>
<td align="center" valign="middle">?</td>
<td align="center" valign="middle">1.07x<br />
1.10x</td>
</tr>
<tr>
<td class="tlgrey">HVM</td>
<td align="center" valign="middle">Q4<br />
2022</td>
<td align="center" valign="middle">Q4<br />
2023</td>
<td align="center" valign="middle">H2<br />
2024</td>
<td align="center" valign="middle">H2<br />
2025</td>
<td align="center" valign="middle">H2<br />
2025</td>
<td align="center" valign="middle">H2<br />
2026</td>
<td align="center" valign="middle">H2<br />
2026</td>
<td align="center" valign="middle">H2<br />
2026</td>
</tr>
</tbody>
</table>
<p><small>*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.<br />
**At the same area. <br />
***At the same speed.</small></p>
<p>The production nodes are N3X (3nm-class, extreme performance-focused) as well as N2 (2nm-class). TSMC says that when compared to N3P, chips made on N3X can either lower power consumption by 7% at the same frequency by lowering Vdd from 1.0V to 0.9V, increase performance by 5% at the same area, or increase transistor density by around 10% at the same frequency. Meanwhile, the key advantage of N3X compared to predecessors is its maximum voltage of 1.2V, which is important for ultra-high-performance applications, such as desktop or datacenter GPUs.</p>
<p>TSMC's N2 will be TSMC's first production node to use gate-all-around (GAA) nanosheet transistors and this will significantly enhance its performance, power, and are... Semiconductors&body=https://compbuddey.blogspot.com/2024/05/tsmcs-roadmap-at-glance-n3x-n2p-a16_29.html){kind=link}
Intel Sells Its Arm Shares, Reduces Stakes in Other Companies 
Intel has divested its entire stake in Arm Holdings during the second quarter, raising approximately $147 million. Alongside this, Intel sold its stake in cybersecurity firm ZeroFox and reduced its holdings in Astera Labs, all as part of a broader effort to manage costs and recover cash amid significant financial challenges.
The sale of Intel's 1.18 million shares in Arm Holdings, as reported in a recent SEC filing, comes at a time when the company is struggling with substantial financial losses. Despite the $147 million generated from the sale, Intel reported a $120 million net loss on its equity investments for the quarter, which is a part of a larger $1.6 billion loss that Intel faced during this period.
In addition to selling its stake in Arm, Intel also exited its investment in ZeroFox and reduced its involvement with Astera Labs, a company known for developing connectivity platforms for enterprise hardware. These moves are in line with Intel's strategy to reduce costs and stabilize its financial position as it faces ongoing market challenges.
Despite the divestment, Intel's past investment in Arm was likely driven by strategic considerations. Arm Holdings is a significant force in the semiconductor industry, with its designs powering most mobile devices, and, for obvious reasons, Intel would like to address these. Intel and Arm are also collaborating on datacenter platforms tailored for Intel's 18A process technology. Additionally, Arm might view Intel as a potential licensee for its technologies and a valuable partner for other companies that license Arm's designs.
Intel's investment in Astera Labs was also a strategic one as the company probably wanted to secure steady supply of smart retimers, smart cable modems, and CXL memory controller, which are used in volumes in datacenters and Intel is certainly interested in selling as many datacenter CPUs as possible.
Intel's financial struggles were highlighted earlier this month when the company released a disappointing earnings report, which led to a 33% drop in its stock value, erasing billions of dollars of capitalization. To counter these difficulties, Intel announced plans to cut 15,000 jobs and implement other expense reductions. The company has also suspended its dividend, signaling the depth of its efforts to conserve cash and focus on recovery. When it comes to divestment of Arm stock, the need for immediate financial stabilization has presumably taken precedence, leading to the decision.
CPUs
Lorem Ipsum is simply dummy text of the printing and typesetting industry. Lorem Ipsum has been the industry's.
Silicon Motion Demonstrates Flexible Data Placement on MonTitan Gen 5 Enterprise SSD Platform
At FMS 2024, the technological requirements from the storage and memory subsystem took center stage. Both SSD and controller vendors had various demonstrations touting their suitability for different stages of the AI data pipeline - ingestion, preparation, training, checkpointing, and inference. Vendors like Solidigm have different types of SSDs optimized for different stages of the pipeline. At the same time, controller vendors have taken advantage of one of the features introduced recently in the NVM Express standard - Flexible Data Placement (FDP).
FDP involves the host providing information / hints about the areas where the controller could place the incoming write data in order to reduce the write amplification. These hints are generated based on specific block sizes advertised by the device. The feature is completely backwards-compatible, with non-FDP hosts working just as before with FDP-enabled SSDs, and vice-versa.
Silicon Motion's MonTitan Gen 5 Enterprise SSD Platform was announced back in 2022. Since then, Silicon Motion has been touting the flexibility of the platform, allowing its customers to incorporate their own features as part of the customization process. This approach is common in the enterprise space, as we have seen with Marvell's Bravera SC5 SSD controller in the DapuStor SSDs and Microchip's Flashtec controllers in the Longsys FORESEE enterprise SSDs.
At FMS 2024, the company was demonstrating the advantages of flexible data placement by allowing a single QLC SSD based on their MonTitan platform to take part in different stages of the AI data pipeline while maintaining the required quality of service (minimum bandwidth) for each process. The company even has a trademarked name (PerformaShape) for the firmware feature in the controller that allows the isolation of different concurrent SSD accesses (from different stages in the AI data pipeline) to guarantee this QoS. Silicon Motion claims that this scheme will enable its customers to get the maximum write performance possible from QLC SSDs without negatively impacting the performance of other types of accesses.
Silicon Motion and Phison have market leadership in the client SSD controller market with similar approaches. However, their enterprise SSD controller marketing couldn't be more different. While Phison has gone in for a turnkey solution with their Gen 5 SSD platform (to the extent of not adopting the white label route for this generation, and instead opting to get the SSDs qualified with different cloud service providers themselves), Silicon Motion is opting for a different approach. The flexibility and customization possibilities can make platforms like the MonTitan appeal to flash array vendors.
Storage
U.S. Signs $1.5B in CHIPS Act Agreements With Amkor and SKhynix for Chip Packaging Plants
Under the CHIPS & Science Act, the U.S. government provided tens of billions of dollars in grants and loans to the world's leading maker of chips, such as Intel, Samsung, and TSMC, which will significantly expand the country's semiconductor production industry in the coming years. However, most chips are typically tested, assembled, and packaged in Asia, which has left the American supply chain incomplete. Addressing this last gap in the government's domestic chip production plans, these past couple of weeks the U.S. government signed memorandums of understanding worth about $1.5 billion with Amkor and SK hynix to support their efforts to build chip packaging facilities in the U.S.
Amkor to Build Advanced Packaging Facility with Apple in Mind
Amkor plans to build a $2 billion advanced packaging facility near Peoria, Arizona, to test and assemble chips produced by TSMC at its Fab 21 near Phoenix, Arizona. The company signed a MOU that offers $400 million in direct funding and access to $200 million in loans under the CHIPS & Science Act. In addition, the company plans to take advantage of a 25% investment tax credit on eligible capital expenditures.
Set to be strategically positioned near TSMC's upcoming Fab 21 complex in Arizona, Amkor's Peoria facility will occupy 55 acres and, when fully completed, will feature over 500,000 square feet (46,451 square meters) of cleanroom space, more than twice the size of Amkor's advanced packaging site in Vietnam. Although the company has not disclosed the exact capacity or the specific technologies the facility will support, it is expected to cater to a wide range of industries, including automotive, high-performance computing, and mobile technologies. This suggests the new plant will offer diverse packaging solutions, including traditional, 2.5D, and 3D technologies.
Amkor has collaborated extensively with Apple on the vision and initial setup of the Peoria facility, as Apple is slated to be the facility's first and largest customer, marking a significant commitment from the tech giant. This partnership highlights the importance of the new facility in reinforcing the U.S. semiconductor supply chain and positioning Amkor as a key partner for companies relying on TSMC's manufacturing capabilities. The project is expected to generate around 2,000 jobs and is scheduled to begin operations in 2027.
SK hynix to Build HBM4 in the U.S.
This week SK hynix also signed a preliminary agreement with the U.S. government to receive up to $450 million in direct funding and $500 million in loans to build an advanced memory packaging facility in West Lafayette, Indiana.
The proposed facility is scheduled to begin operations in 2028, which means that it will assemble HBM4 or HBM4E memory. Meanwhile, DRAM devices for high bandwidth memory (HBM) stacks will still be produced in South Korea. Nonetheless, packing finished HBM4/HBM4E in the U.S. and possibly integrating these memory modules with high-end processors is a big deal.
In addition to building its packaging plant, SK hynix plans to collaborate with Purdue University and other local research institutions to advance semiconductor technology and packaging innovations. This partnership is intended to bolster research and development in the region, positioning the facility as a hub for AI technology and skilled employment.
Semiconductors
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