Samsung Foundry Update: 2nm Unveil in June, Second-Gen SF3 3nm Hits Production This Year
As part of Samsung's Q1 earnings announcement, the company has outlined some of its foundry unit's key plans for the rest of the year. The company has confirmed that it remains on track to meeting its goal of starting mass production of chips on its SF3 (3 nm-class, 2nd Generation) technology in the second half of the year. Meanwhile in June, Samsung Foundry will formally unveil its SF2 (2 nm-class) process technology, which will offer a mix of performance and efficiency enhancements. Finally, the company the company is preparing a variation of its 4 nm-class technology for integration into stacked 3D designs.
SF2 To Be Unveiled In June
Samsung plans to disclose key details about its SF2 fabrication technology at the VLSI Symposium 2024 on June 19. This will be the company's second major process node based upon gate-all-around (GAA) multi-bridge channel field-effect transistors (MBCFET). Improving over its predecessor, SF2 will feature a 'unique epitaxial and integration process,' which will give the process node higher performance and lower leakage than traditional FinFET-based nodes (though Samsung isn't disclosing the specific node they're comparing it to).
Samsung says that SF2 increases performance of narrow transistors by 29% for N-type and 46% for P-type, and wide transistors by 11% and 23% respectively. Moreover, it reduces transistor global variation by 26% compared to FinFET technology, and cuts product leakage by approximately 50%. This process also sets the stage for future advancements in technology through enhanced design technology co-optimization (DTCO) collaboration with its customers.
One thing that Samsung has not mentioned in context of SF2 is backside power delivery, so at least for the moment, there is no indication that Samsung will be adopting this next-gen power routing feature for SF2.
Samsung says that the design infrastructure for SF2 – the PDK, EDA tools, and licensed IP – will be finalized in the second quarter of 2024. Once this happens, Samsung's chip development partners will be able to begin designing products for this production node. Meanwhile, Samsung is already working with Arm to co-optimize Arm's Cortex cores for the SF2 process.
SF3: On Track for 2H 2024
As the first fab to introduce a GAAFET-based node, Samsung has been on the cutting edge of chip construction. At the same time, however, that has also meant that they're the first fab to encounter and solve the inevitable teething issues that come with such a major transistor design change. Consequently, while Samsung's first-generation SF3E process technology has been in production for a little less than two years now, the only publicly-disclosed chips made on the process so far have been relatively small cryptocurrency mining chips – exactly the kind of pipecleaner parts that do well on a new process node.
But with that experience in hand, Samsung is preparing to move on to making bigger and better chips with GAAFETs. As part of their earnings announcements, the company has confirmed that their updated SF3 node, which was introduced last year, remains on schedule to enter production in the second half of 2024.
A more mature product from the get-go, SF3 is being prepared to be used for building larger processors, including datacenter products. Compared to its direct predecessor, SF4, SF3 promises a 22% performance boost at the same power and transistor count, or a 34% lower power at the same frequency and complexity, as well as a 21% logic area reduction. In general, Samsung pins a lot of hopes on this technology, as it's this generation of their 3nm-class technology that is poised to compete against TSMC's N3B and N3E nodes.
SF4: Ready for 3D Stacking
Finally, Samsung is also preparing a variant of their final FinFET technology node, SF4, for use in 3D chiplet stacking. As transistor density improvements have continued to slow, 3D chip stacking has emerged as a way to keep boosting overall chip performance, especially with modern, multi-tile processor desig... Semiconductors
Posted by The Techinical Support
Kioxia Demonstrates Optical Interface SSDs for Data Centers 
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
End of the Road: An AnandTech Farewell It is with great sadness that I find myself penning the hardest news post I’ve ever needed to write here at AnandTech. After over 27 years of covering the wide – and wild – world of computing hardware, today is AnandTech’s final day of publication.
For better or worse, we’ve reached the end of a long journey – one that started with a review of an AMD processor, and has ended with the review of an AMD processor. It’s fittingly poetic, but it is also a testament to the fact that we’ve spent the last 27 years doing what we love, covering the chips that are the lifeblood of the computing industry.
A lot of things have changed in the last quarter-century – in 1997 NVIDIA had yet to even coin the term “GPU” – and we’ve been fortunate to watch the world of hardware continue to evolve over the time period. We’ve gone from boxy desktop computers and laptops that today we’d charitably classify as portable desktops, to pocket computers where even the cheapest budget device puts the fastest PC of 1997 to shame.
The years have also brought some monumental changes to the world of publishing. AnandTech was hardly the first hardware enthusiast website, nor will we be the last. But we were fortunate to thrive in the past couple of decades, when so many of our peers did not, thanks to a combination of hard work, strategic investments in people and products, even more hard work, and the support of our many friends, colleagues, and readers.
Still, few things last forever, and the market for written tech journalism is not what it once was – nor will it ever be again. So, the time has come for AnandTech to wrap up its work, and let the next generation of tech journalists take their place within the zeitgeist.
It has been my immense privilege to write for AnandTech for the past 19 years – and to manage it as its editor-in-chief for the past decade. And while I carry more than a bit of remorse in being AnandTech’s final boss, I can at least take pride in everything we’ve accomplished over the years, whether it’s lauding some legendary products, writing technology primers that still remain relevant today, or watching new stars rise in expected places. There is still more that I had wanted AnandTech to do, but after 21,500 articles, this was a good start.
And while the AnandTech staff is riding off into the sunset, I am happy to report that the site itself won’t be going anywhere for a while. Our publisher, Future PLC, will be keeping the AnandTech website and its many articles live indefinitely. So that all of the content we’ve created over the years remains accessible and citable. Even without new articles to add to the collection, I expect that many of the things we’ve written over the past couple of decades will remain relevant for years to come – and remain accessible just as long.
The AnandTech Forums will also continue to be operated by Future’s community team and our dedicated troop of moderators. With forum threads going back to 1999 (and some active members just as long), the forums have a history almost as long and as storied as AnandTech itself (wounded monitor children, anyone?). So even when AnandTech is no longer publishing articles, we’ll still have a place for everyone to talk about the latest in technology – and have those discussions last longer than 48 hours.
Finally, for everyone who still needs their technical writing fix, our formidable opposition of the last 27 years and fellow Future brand, Tom’s Hardware, is continuing to cover the world of technology. There are a couple of familiar AnandTech faces already over there providing their accumulated expertise, and the site will continue doing its best to provide a written take on technology news.
So Many Thank Yous
As I look back on everything AnandTech has accomplished over the past 27 years, there are more than a few people, groups, and companies that I would like to thank on behalf of both myself and AnandTech as a whole.
First and foremost, I cannot thank enough all the editors who have worked for AnandTech over the years. T... Site Updates
![](https://twitter.com/share?url=https://compbuddey.blogspot.com/2024/05/samsung-foundry-update-2nm-unveil-in_16.html&text=Samsung Foundry Update: 2nm Unveil in June, Second-Gen SF3 3nm Hits Production This Year <p align="center"><a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year"><img src="https://images.anandtech.com/doci/21377/samsung-foundry-wafer-semiconductor-678-1_575px.jpg" alt="" /></a></p><p><p>As part of Samsung's Q1 earnings announcement, the company has outlined some of its foundry unit's key plans for the rest of the year. The company has confirmed that it remains on track to meeting its goal of starting mass production of chips on its SF3 (3 nm-class, 2nd Generation) technology in the second half of the year. Meanwhile in June, Samsung Foundry will formally unveil its SF2 (2 nm-class) process technology, which will offer a mix of performance and efficiency enhancements. Finally, the company the company is preparing a variation of its 4 nm-class technology for integration into stacked 3D designs.</p>
<h3>SF2 To Be Unveiled In June</h3>
<p>Samsung plans to disclose key details about its SF2 fabrication technology at the VLSI Symposium 2024 on June 19. This will be the company's second major process node based upon gate-all-around (GAA) multi-bridge channel field-effect transistors (MBCFET). Improving over its predecessor, SF2 will feature a 'unique epitaxial and integration process,' which will give the process node higher performance and lower leakage than traditional FinFET-based nodes (though Samsung isn't disclosing the specific node they're comparing it to).</p>
<p style="text-align: center;"><a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year"><img alt="" src="https://images.anandtech.com/doci/21377/samsung-foundry-roadmap.png" style="width: 100%;" /></a></p>
<p>Samsung says that SF2 increases performance of narrow transistors by 29% for N-type and 46% for P-type, and wide transistors by 11% and 23% respectively. Moreover, it reduces transistor global variation by 26% compared to FinFET technology, and cuts product leakage by approximately 50%. This process also sets the stage for future advancements in technology through enhanced design technology co-optimization (DTCO) collaboration with its customers.</p>
<p>One thing that Samsung has not mentioned in context of SF2 is backside power delivery, so at least for the moment, there is no indication that Samsung will be adopting this next-gen power routing feature for SF2.</p>
<p>Samsung says that the design infrastructure for SF2 – the PDK, EDA tools, and licensed IP – will be finalized in the second quarter of 2024. Once this happens, Samsung's chip development partners will be able to begin designing products for this production node. Meanwhile, Samsung is already working with Arm to co-optimize Arm's Cortex cores for the SF2 process.</p>
<h3>SF3: On Track for 2H 2024</h3>
<p>As the first fab to introduce a GAAFET-based node, Samsung has been on the cutting edge of chip construction. At the same time, however, that has also meant that they're the first fab to encounter and solve the inevitable teething issues that come with such a major transistor design change. Consequently, while Samsung's first-generation SF3E process technology has been in production for a little less than two years now, the only publicly-disclosed chips made on the process so far have been relatively small cryptocurrency mining chips – exactly the kind of pipecleaner parts that do well on a new process node.</p>
<p>But with that experience in hand, Samsung is preparing to move on to making bigger and better chips with GAAFETs. As part of their earnings announcements, the company has confirmed that their updated SF3 node, which was introduced last year, remains on schedule to enter production in the second half of 2024.</p>
<p align="center"><a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year"><img alt="" src="https://images.anandtech.com/doci/21377/Samsung_Q1_Foundry.png" style="width: 100%;" /></a></p>
<p>A more mature product from the get-go, SF3 is being prepared to be used for building larger processors, including datacenter products. Compared to its direct predecessor, SF4, SF3 promises a 22% performance boost at the same power and transistor count, or a 34% lower power at the same frequency and complexity, as well as a 21% logic area reduction. In general, Samsung pins a lot of hopes on this technology, as it's this generation of their 3nm-class technology that is poised to compete against TSMC's N3B and N3E nodes.</p>
<h3>SF4: Ready for 3D Stacking</h3>
<p>Finally, Samsung is also preparing a variant of their final FinFET technology node, SF4, for use in 3D chiplet stacking. As transistor density improvements have continued to slow, 3D chip stacking has emerged as a way to keep boosting overall chip performance, especially with modern, multi-tile processor desig... Semiconductors){kind=link}
![](https://www.pinterest.com/pin/create/button/?url=https://compbuddey.blogspot.com/2024/05/samsung-foundry-update-2nm-unveil-in_16.html&media=https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_udPQftfNkNHZdVBraPVaRU0G-KHHc-ytErdLwYB5t_XRxiu9UG28M7WSYAy3AOKlPvbH_raBjbDXAiMxGPyJlJuz5QnbBmu6Hm31X9V9yxRTr5HpqJO5vXIkXvw30nOIaS45rEMhES7FaJARNH7Iqp-Ujj3WT2snOR1tnSkxg&description=Samsung Foundry Update: 2nm Unveil in June, Second-Gen SF3 3nm Hits Production This Year <p align="center"><a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year"><img src="https://images.anandtech.com/doci/21377/samsung-foundry-wafer-semiconductor-678-1_575px.jpg" alt="" /></a></p><p><p>As part of Samsung's Q1 earnings announcement, the company has outlined some of its foundry unit's key plans for the rest of the year. The company has confirmed that it remains on track to meeting its goal of starting mass production of chips on its SF3 (3 nm-class, 2nd Generation) technology in the second half of the year. Meanwhile in June, Samsung Foundry will formally unveil its SF2 (2 nm-class) process technology, which will offer a mix of performance and efficiency enhancements. Finally, the company the company is preparing a variation of its 4 nm-class technology for integration into stacked 3D designs.</p>
<h3>SF2 To Be Unveiled In June</h3>
<p>Samsung plans to disclose key details about its SF2 fabrication technology at the VLSI Symposium 2024 on June 19. This will be the company's second major process node based upon gate-all-around (GAA) multi-bridge channel field-effect transistors (MBCFET). Improving over its predecessor, SF2 will feature a 'unique epitaxial and integration process,' which will give the process node higher performance and lower leakage than traditional FinFET-based nodes (though Samsung isn't disclosing the specific node they're comparing it to).</p>
<p style="text-align: center;"><a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year"><img alt="" src="https://images.anandtech.com/doci/21377/samsung-foundry-roadmap.png" style="width: 100%;" /></a></p>
<p>Samsung says that SF2 increases performance of narrow transistors by 29% for N-type and 46% for P-type, and wide transistors by 11% and 23% respectively. Moreover, it reduces transistor global variation by 26% compared to FinFET technology, and cuts product leakage by approximately 50%. This process also sets the stage for future advancements in technology through enhanced design technology co-optimization (DTCO) collaboration with its customers.</p>
<p>One thing that Samsung has not mentioned in context of SF2 is backside power delivery, so at least for the moment, there is no indication that Samsung will be adopting this next-gen power routing feature for SF2.</p>
<p>Samsung says that the design infrastructure for SF2 – the PDK, EDA tools, and licensed IP – will be finalized in the second quarter of 2024. Once this happens, Samsung's chip development partners will be able to begin designing products for this production node. Meanwhile, Samsung is already working with Arm to co-optimize Arm's Cortex cores for the SF2 process.</p>
<h3>SF3: On Track for 2H 2024</h3>
<p>As the first fab to introduce a GAAFET-based node, Samsung has been on the cutting edge of chip construction. At the same time, however, that has also meant that they're the first fab to encounter and solve the inevitable teething issues that come with such a major transistor design change. Consequently, while Samsung's first-generation SF3E process technology has been in production for a little less than two years now, the only publicly-disclosed chips made on the process so far have been relatively small cryptocurrency mining chips – exactly the kind of pipecleaner parts that do well on a new process node.</p>
<p>But with that experience in hand, Samsung is preparing to move on to making bigger and better chips with GAAFETs. As part of their earnings announcements, the company has confirmed that their updated SF3 node, which was introduced last year, remains on schedule to enter production in the second half of 2024.</p>
<p align="center"><a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year"><img alt="" src="https://images.anandtech.com/doci/21377/Samsung_Q1_Foundry.png" style="width: 100%;" /></a></p>
<p>A more mature product from the get-go, SF3 is being prepared to be used for building larger processors, including datacenter products. Compared to its direct predecessor, SF4, SF3 promises a 22% performance boost at the same power and transistor count, or a 34% lower power at the same frequency and complexity, as well as a 21% logic area reduction. In general, Samsung pins a lot of hopes on this technology, as it's this generation of their 3nm-class technology that is poised to compete against TSMC's N3B and N3E nodes.</p>
<h3>SF4: Ready for 3D Stacking</h3>
<p>Finally, Samsung is also preparing a variant of their final FinFET technology node, SF4, for use in 3D chiplet stacking. As transistor density improvements have continued to slow, 3D chip stacking has emerged as a way to keep boosting overall chip performance, especially with modern, multi-tile processor desig... Semiconductors){kind=link}
![](https://web.whatsapp.com/send?text=Samsung Foundry Update: 2nm Unveil in June, Second-Gen SF3 3nm Hits Production This Year <p align="center"><a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year"><img src="https://images.anandtech.com/doci/21377/samsung-foundry-wafer-semiconductor-678-1_575px.jpg" alt="" /></a></p><p><p>As part of Samsung's Q1 earnings announcement, the company has outlined some of its foundry unit's key plans for the rest of the year. The company has confirmed that it remains on track to meeting its goal of starting mass production of chips on its SF3 (3 nm-class, 2nd Generation) technology in the second half of the year. Meanwhile in June, Samsung Foundry will formally unveil its SF2 (2 nm-class) process technology, which will offer a mix of performance and efficiency enhancements. Finally, the company the company is preparing a variation of its 4 nm-class technology for integration into stacked 3D designs.</p>
<h3>SF2 To Be Unveiled In June</h3>
<p>Samsung plans to disclose key details about its SF2 fabrication technology at the VLSI Symposium 2024 on June 19. This will be the company's second major process node based upon gate-all-around (GAA) multi-bridge channel field-effect transistors (MBCFET). Improving over its predecessor, SF2 will feature a 'unique epitaxial and integration process,' which will give the process node higher performance and lower leakage than traditional FinFET-based nodes (though Samsung isn't disclosing the specific node they're comparing it to).</p>
<p style="text-align: center;"><a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year"><img alt="" src="https://images.anandtech.com/doci/21377/samsung-foundry-roadmap.png" style="width: 100%;" /></a></p>
<p>Samsung says that SF2 increases performance of narrow transistors by 29% for N-type and 46% for P-type, and wide transistors by 11% and 23% respectively. Moreover, it reduces transistor global variation by 26% compared to FinFET technology, and cuts product leakage by approximately 50%. This process also sets the stage for future advancements in technology through enhanced design technology co-optimization (DTCO) collaboration with its customers.</p>
<p>One thing that Samsung has not mentioned in context of SF2 is backside power delivery, so at least for the moment, there is no indication that Samsung will be adopting this next-gen power routing feature for SF2.</p>
<p>Samsung says that the design infrastructure for SF2 – the PDK, EDA tools, and licensed IP – will be finalized in the second quarter of 2024. Once this happens, Samsung's chip development partners will be able to begin designing products for this production node. Meanwhile, Samsung is already working with Arm to co-optimize Arm's Cortex cores for the SF2 process.</p>
<h3>SF3: On Track for 2H 2024</h3>
<p>As the first fab to introduce a GAAFET-based node, Samsung has been on the cutting edge of chip construction. At the same time, however, that has also meant that they're the first fab to encounter and solve the inevitable teething issues that come with such a major transistor design change. Consequently, while Samsung's first-generation SF3E process technology has been in production for a little less than two years now, the only publicly-disclosed chips made on the process so far have been relatively small cryptocurrency mining chips – exactly the kind of pipecleaner parts that do well on a new process node.</p>
<p>But with that experience in hand, Samsung is preparing to move on to making bigger and better chips with GAAFETs. As part of their earnings announcements, the company has confirmed that their updated SF3 node, which was introduced last year, remains on schedule to enter production in the second half of 2024.</p>
<p align="center"><a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year"><img alt="" src="https://images.anandtech.com/doci/21377/Samsung_Q1_Foundry.png" style="width: 100%;" /></a></p>
<p>A more mature product from the get-go, SF3 is being prepared to be used for building larger processors, including datacenter products. Compared to its direct predecessor, SF4, SF3 promises a 22% performance boost at the same power and transistor count, or a 34% lower power at the same frequency and complexity, as well as a 21% logic area reduction. In general, Samsung pins a lot of hopes on this technology, as it's this generation of their 3nm-class technology that is poised to compete against TSMC's N3B and N3E nodes.</p>
<h3>SF4: Ready for 3D Stacking</h3>
<p>Finally, Samsung is also preparing a variant of their final FinFET technology node, SF4, for use in 3D chiplet stacking. As transistor density improvements have continued to slow, 3D chip stacking has emerged as a way to keep boosting overall chip performance, especially with modern, multi-tile processor desig... Semiconductors | https://compbuddey.blogspot.com/2024/05/samsung-foundry-update-2nm-unveil-in_16.html){kind=link}
![](mailto:?subject=Samsung Foundry Update: 2nm Unveil in June, Second-Gen SF3 3nm Hits Production This Year <p align="center"><a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year"><img src="https://images.anandtech.com/doci/21377/samsung-foundry-wafer-semiconductor-678-1_575px.jpg" alt="" /></a></p><p><p>As part of Samsung's Q1 earnings announcement, the company has outlined some of its foundry unit's key plans for the rest of the year. The company has confirmed that it remains on track to meeting its goal of starting mass production of chips on its SF3 (3 nm-class, 2nd Generation) technology in the second half of the year. Meanwhile in June, Samsung Foundry will formally unveil its SF2 (2 nm-class) process technology, which will offer a mix of performance and efficiency enhancements. Finally, the company the company is preparing a variation of its 4 nm-class technology for integration into stacked 3D designs.</p>
<h3>SF2 To Be Unveiled In June</h3>
<p>Samsung plans to disclose key details about its SF2 fabrication technology at the VLSI Symposium 2024 on June 19. This will be the company's second major process node based upon gate-all-around (GAA) multi-bridge channel field-effect transistors (MBCFET). Improving over its predecessor, SF2 will feature a 'unique epitaxial and integration process,' which will give the process node higher performance and lower leakage than traditional FinFET-based nodes (though Samsung isn't disclosing the specific node they're comparing it to).</p>
<p style="text-align: center;"><a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year"><img alt="" src="https://images.anandtech.com/doci/21377/samsung-foundry-roadmap.png" style="width: 100%;" /></a></p>
<p>Samsung says that SF2 increases performance of narrow transistors by 29% for N-type and 46% for P-type, and wide transistors by 11% and 23% respectively. Moreover, it reduces transistor global variation by 26% compared to FinFET technology, and cuts product leakage by approximately 50%. This process also sets the stage for future advancements in technology through enhanced design technology co-optimization (DTCO) collaboration with its customers.</p>
<p>One thing that Samsung has not mentioned in context of SF2 is backside power delivery, so at least for the moment, there is no indication that Samsung will be adopting this next-gen power routing feature for SF2.</p>
<p>Samsung says that the design infrastructure for SF2 – the PDK, EDA tools, and licensed IP – will be finalized in the second quarter of 2024. Once this happens, Samsung's chip development partners will be able to begin designing products for this production node. Meanwhile, Samsung is already working with Arm to co-optimize Arm's Cortex cores for the SF2 process.</p>
<h3>SF3: On Track for 2H 2024</h3>
<p>As the first fab to introduce a GAAFET-based node, Samsung has been on the cutting edge of chip construction. At the same time, however, that has also meant that they're the first fab to encounter and solve the inevitable teething issues that come with such a major transistor design change. Consequently, while Samsung's first-generation SF3E process technology has been in production for a little less than two years now, the only publicly-disclosed chips made on the process so far have been relatively small cryptocurrency mining chips – exactly the kind of pipecleaner parts that do well on a new process node.</p>
<p>But with that experience in hand, Samsung is preparing to move on to making bigger and better chips with GAAFETs. As part of their earnings announcements, the company has confirmed that their updated SF3 node, which was introduced last year, remains on schedule to enter production in the second half of 2024.</p>
<p align="center"><a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year"><img alt="" src="https://images.anandtech.com/doci/21377/Samsung_Q1_Foundry.png" style="width: 100%;" /></a></p>
<p>A more mature product from the get-go, SF3 is being prepared to be used for building larger processors, including datacenter products. Compared to its direct predecessor, SF4, SF3 promises a 22% performance boost at the same power and transistor count, or a 34% lower power at the same frequency and complexity, as well as a 21% logic area reduction. In general, Samsung pins a lot of hopes on this technology, as it's this generation of their 3nm-class technology that is poised to compete against TSMC's N3B and N3E nodes.</p>
<h3>SF4: Ready for 3D Stacking</h3>
<p>Finally, Samsung is also preparing a variant of their final FinFET technology node, SF4, for use in 3D chiplet stacking. As transistor density improvements have continued to slow, 3D chip stacking has emerged as a way to keep boosting overall chip performance, especially with modern, multi-tile processor desig... Semiconductors&body=https://compbuddey.blogspot.com/2024/05/samsung-foundry-update-2nm-unveil-in_16.html){kind=link}
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
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Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
Kioxia Demonstrates Optical Interface SSDs for Data Centers
A few years back, the Japanese government's New Energy and Industrial Technology Development Organization (NEDO ) allocated funding for the development of green datacenter technologies. With the aim to obtain up to 40% savings in overall power consumption, several Japanese companies have been developing an optical interface for their enterprise SSDs. And at this year's FMS, Kioxia had their optical interface on display.
For this demonstration, Kioxia took its existing CM7 enterprise SSD and created an optical interface for it. A PCIe card with on-board optics developed by Kyocera is installed in the server slot. An optical interface allows data transfer over long distances (it was 40m in the demo, but Kioxia promises lengths of up to 100m for the cable in the future). This allows the storage to be kept in a separate room with minimal cooling requirements compared to the rack with the CPUs and GPUs. Disaggregation of different server components will become an option as very high throughput interfaces such as PCIe 7.0 (with 128 GT/s rates) become available.
The demonstration of the optical SSD showed a slight loss in IOPS performance, but a significant advantage in the latency metric over the shipping enterprise SSD behind a copper network link. Obviously, there are advantages in wiring requirements and signal integrity maintenance with optical links.
Being a proof-of-concept demonstration, we do see the requirement for an industry-standard approach if this were to gain adoption among different datacenter vendors. The PCI-SIG optical workgroup will need to get its act together soon to create a standards-based approach to this problem.
Storage
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