Google Develops In-House Arm 'Axion' CPU for Datacenters
Google was among the first hyperscalers build custom silicon for its services, starting first with tensor processing units (TPUs) for its AI initiatives, and then video transcoding units (VCUs) for the YouTube service. But unlike its industry peers, the company has been slower to adopt custom CPU designs, prefering to stick to off-the-shelf chips from the major CPUs. This is finally changing at Google, with the announcement that the company has developed its own in-house datacenter CPU, the Axion.
Google's Axion processor is based on the Arm Neoverse V2 (Arm v9) platform, which is Arm's current-generation design for high-performance server CPUs, and is already employed in other chips such as NVIDIA's Grace and Amazon's Graviton4. Within Google, Axion is aimed at a wide variety of workloads, including web and app servers, data analytics, microservices, and AI training. Google claims that the Axion processors boast up to 50% higher performance and up to 60% better energy efficiency compared to current-generation x86-based processors, as well as offer a 30% higher performance compared to competing Arm-based CPUs for datacenters. Though as is increasingly common for the cryptic cloud side of Google's business, least for now the company isn't specifying what processors they're comparing Axion to in these metrics.
While Google is not disclosing core counts or the full specifications of its Axion CPUs, the company is revealing that they are incorporating their own secret sauce into the silicon in the form of the company's Titanium purpose-built microcontrollers. These microcontrollers are designed to handle basic operations like networking and security, as well as offload storage I/O processing to Hyperdisk block storage service. As a result of this offloading, virtually all of the CPU core resources should be available to actual workloads. As for the chip's memory subsystem, Axion uses conventional dual-rank DDR5 memory modules.
"Google's announcement of the new Axion CPU marks a significant milestone in delivering custom silicon that is optimized for Google's infrastructure, and built on our high-performance Arm Neoverse V2 platform," said Rene Haas, CEO of Arm. "Decades of ecosystem investment, combined with Google's ongoing innovation and open-source software contributions ensure the best experience for the workloads that matter most to customers running on Arm everywhere."
Google has previously deployed Arm-based processors for its own services, including BigTable, Spanner, BigQuery, and YouTube Ads and is ready to offer instances based on its Armv9-based Axion CPUs to its customers that can use software developed for Arm architectures.
Sources: Google, Wall Street Journal
CPUs
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![TSMC to Expand Specialty Capacity by 50%, Introduce 4nm N4e Low-Power Node <p align="center"><a href="https://www.anandtech.com/show/21397/tsmc-to-expand-specialty-capacity-by-50-introduce-4nm-lowpower-node"><img src="https://images.anandtech.com/doci/21397/tsmc-semiconductor-fab-wafer-1-678_575px.jpg" alt="" /></a></p><p><p>With all the new fabs being built in Germany and Japan, as well as the expansion of production capacity in China, TSMC is planning to extend its production capacity for specialty technologies by 50% by 2027. As disclosed by the company during its European Technology Symposium this week, TSMC expects to need to not only convert existing capacity to meet demands for specialty processes, but even build new (greenfield) fab space just for this purpose. One of the big drivers for this demand, in turn, will be TSMC's next specialty node: N4e, a 4nm-class ultra-low-power production node.</p>
<p>"In the past, we always did the review phase [for upcoming fabs], but for the first time in a long time at TSMC, we started building greenfield fab that will address the future specialty technology requirements," said Dr. Kevin Zhang, Senior Vice President, Business Development and Overseas Operations Office, at the event. "In the next four to five years, we actually going to grow our specialty capacity by up to 1.5x. In doing so we actually expanding the footprint of our manufacturing network to improve the resiliency of the overall fab supply chain."</p>
<p>On top of its well-known major logic nodes like N5 and N3E, TSMC also offers a suite of specialty nodes for applications such as power semiconductors, mixed analog I/O, and ultra-low-power applications (e.g. IoT). These are typically based on the company's trailing manufacturing processes, but regardless of the underlying technology, the capacity demand for these nodes is growing right alongside the demand for TSMC's major logic nodes. All of which has required TSMC to reevaluate how they go about planning for capacity on their specialty nodes.</p>
<p>TSMC's expansion strategy in the recent years has pursued several goals. One of them has been to build new fabs outside of Taiwan; another has been to generally expand production capacity to meet future demand for all types of process technologies – which is why the company is building up capacity for specialty nodes.</p>
<p>At present, TSMC's most advanced specialty node is N6e, an N7/N6 variant that supports operating voltages between 0.4V and 0.9V. With N4e, TSMC is looking at voltages below 0.4V. Though for now, TSMC is not disclosing much in the way of technical details for the planned node; given the company's history here, we expect they'll have more to talk about next year once the new process is ready.</p>
</p> Semiconductors](https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_uCBQ5v1xEp0__XaRU5_8j42yHaZSFyzV1IDtag-sO1rtIdvgfZ4pIoSvsneMgNyWn6whnsjyiKuffGTPfYuyn61SzK7_iXCP_DWbRpFgxFthGhIk3MDfSSETKiS6csS09r2bA-f-4ms28OSh814fzPebdNuyDcRA=w72-h72-p-k-no-nu)
Micron Ships Crucial-Branded LPCAMM2 Memory Modules: 64GB of LPDDR5X For $330 
As LPCAMM2 adoption begins, the first retail memory modules are finally starting to hit the retail market, courtesy of Micron. The memory manufacturer has begun selling their LPDDR5X-based LPCAMM2 memory modules under their in-house Crucial brand, making them available on the latter's storefront. Timed to coincide with the release of Lenovo's ThinkPad P1 Gen 7 laptop – the first retail laptop designed to use the memory modules – this marks the de facto start of the eagerly-awaited modular LPDDR5X memory era.
Micron's Low Power Compression Attached Memory Module 2 (LPCAMM2) modules are available in capacities of 32 GB and 64 GB. These are dual-channel modules that feature a 128-bit wide interface, and are based around LPDDR5X memory running at data rates up to 7500 MT/s. This gives a single LPCAMM2 a peak bandwidth of 120 GB/s. Micron is not disclosing the latencies of its LPCAMM2 memory modules, but it says that high data transfer rates of LPDDR5X compensate for the extended timings.
Micron says that LPDDR5X memory offers significantly lower power consumption, with active power per 64-bit bus being 43-58% lower than DDR5 at the same speed, and standby power up to 80% lower. Meanwhile, similar to DDR5 modules, LPCAMM2 modules include a power management IC and voltage regulating circuitry, which provides module manufacturers additional opportunities to reduce power consumption of their products.
Source: Micron LPDDR5X LPCAMM2 Technical Brief
It's worth noting, however, that at least for the first generation of LPCAMM2 modules, system vendors will need to pick between modularity and performance. While soldered-down LPDDR5X memory is available at speeds up to 8533 MT/sec – and with 9600 MT/sec on the horizon – the fastest LPCAMM2 modules planned for this year by both Micron and rival Samsung will be running at 7500 MT/sec. So vendors will have to choose between the flexibility of offering modular LPDDR5X, or the higher bandwidth (and space savings) offered by soldering down their memory.
Micron, for its part, is projecting that 9600 MT/sec LPCAMM2 modules will be available by 2026. Though it's all but certain that faster memory will also be avaialble in the same timeframe.
Micron's Crucial LPDDR5X 32 GB module costs $174.99, whereas a 64 GB module costs $329.99.
Memory
Source: Micron LPDDR5X LPCAMM2 Technical Brief
CUDIMM Standard Set to Make Desktop Memory a Bit Smarter and a Lot More Robust While the new CAMM and LPCAMM memory modules for laptops have garnered a great deal of attention in recent months, it's not just the mobile side of the PC memory industry that is looking at changes. The desktop memory market is also coming due for some upgrades to further improve DIMM performance, in the form of a new DIMM variety called the Clocked Unbuffered DIMM (CUDIMM). And while this memory isn't in use quite yet, several memory vendors had their initial CUDIMM products on display at this year's Computex trade show, offering a glimpse into the future of desktop memory.
A variation on traditional Unbuffered DIMMs (UDIMMs), Clocked UDIMMs (and Clocked SODIMMs) have been created as another solution to the ongoing signal integrity challenges presented by DDR5 memory. DDR5 allows for rather speedy transfer rates with removable (and easily installed) DIMMs, but further performance increases are running up against the laws of physics when it comes to the electrical challenges of supporting memory on a stick – particularly with so many capacity/performance combinations like we see today. And while those challenges aren't insurmountable, if DDR5 (and eventually, DDR6) are to keep increasing in speed, some changes appear to be needed to produce more electrically robust DIMMs, which is giving rise to the CUDIMM.
Standardized by JEDEC earlier this year as JESD323, CUDIMMs tweak the traditional unbuffered DIMM by adding a clock driver (CKD) to the DIMM itself, with the tiny IC responsible for regenerating the clock signal driving the actual memory chips. By generating a clean clock locally on the DIMM (rather than directly using the clock from the CPU, as is the case today), CUDIMMs are designed to offer improved stability and reliability at high memory speeds, combating the electrical issues that would otherwise cause reliability issues at faster memory speeds. In other words, adding a clock driver is the key to keeping DDR5 operating reliably at high clockspeeds.
All told, JEDEC is proposing that CUDIMMs be used for DDR5-6400 speeds and higher, with the first version of the specification covering speeds up to DDR5-7200. The new DIMMs will also be drop-in compatible with existing platforms (at least on paper), using the same 288-pin connector as today's standard DDR5 UDIMM and allowing for a relatively smooth transition towards higher DDR5 clockspeeds.
Memory
![](https://twitter.com/share?url=https://compbuddey.blogspot.com/2024/04/google-develops-in-house-arm-axion-cpu_14.html&text=Google Develops In-House Arm 'Axion' CPU for Datacenters <p align="center"><a href="https://www.anandtech.com/show/21343/google-develops-inhouse-axion-cpu-for-datacenters"><img src="https://images.anandtech.com/doci/21343/google-axion-678_575px.jpg" alt="" /></a></p><p><p>Google was among the first hyperscalers build custom silicon for its services, starting first with tensor processing units (TPUs) for its AI initiatives, and then <a href="https://www.tomshardware.com/news/intel-replaces-xeons-with-custom-vcus">video transcoding units (VCUs)</a> for the YouTube service. But unlike its industry peers, the company has been slower to adopt custom CPU designs, prefering to stick to off-the-shelf chips from the major CPUs. This is finally changing at Google, with the announcement that the company has developed its own in-house datacenter CPU, the Axion.</p>
<p>Google's Axion processor is based on the <a href="https://www.anandtech.com/show/17575/arm-announces-neoverse-v2-and-e2-the-next-generation-of-arm-server-cpu-cores">Arm Neoverse V2</a> (Arm v9) platform, which is Arm's current-generation design for high-performance server CPUs, and is already employed in other chips such as NVIDIA's Grace and Amazon's Graviton4. Within Google, Axion is aimed at a wide variety of workloads, including web and app servers, data analytics, microservices, and AI training. Google claims that the Axion processors boast up to 50% higher performance and up to 60% better energy efficiency compared to current-generation x86-based processors, as well as offer a 30% higher performance compared to competing Arm-based CPUs for datacenters. Though as is increasingly common for the cryptic cloud side of Google's business, least for now the company isn't specifying what processors they're comparing Axion to in these metrics.</p>
<p>While Google is not disclosing core counts or the full specifications of its Axion CPUs, the company is revealing that they are incorporating their own secret sauce into the silicon in the form of the company's <a href="https://cloud.google.com/titanium?e=48754805&hl=en">Titanium</a> purpose-built microcontrollers. These microcontrollers are designed to handle basic operations like networking and security, as well as offload storage I/O processing to Hyperdisk block storage service. As a result of this offloading, virtually all of the CPU core resources should be available to actual workloads. As for the chip's memory subsystem, Axion uses conventional dual-rank DDR5 memory modules.</p>
<p>"Google's announcement of the new Axion CPU marks a significant milestone in delivering custom silicon that is optimized for Google's infrastructure, and built on our high-performance Arm Neoverse V2 platform," said Rene Haas, CEO of Arm. "Decades of ecosystem investment, combined with Google's ongoing innovation and open-source software contributions ensure the best experience for the workloads that matter most to customers running on Arm everywhere." </p>
<p>Google has previously deployed Arm-based processors for its own services, including BigTable, Spanner, BigQuery, and YouTube Ads and is ready to offer instances based on its Armv9-based Axion CPUs to its customers that can use software developed for Arm architectures.</p>
<p>Sources: <a href="https://cloud.google.com/blog/products/compute/introducing-googles-new-arm-based-cpu">Google</a>, <a href="https://www.wsj.com/tech/google-expands-in-house-chip-efforts-in-costly-ai-battle-3121c852?st=6010gt7v4bee9ve&reflink=desktopwebshare_permalink&s=31">Wall Street Journal</a></p>
</p> CPUs){kind=link}
![](https://www.pinterest.com/pin/create/button/?url=https://compbuddey.blogspot.com/2024/04/google-develops-in-house-arm-axion-cpu_14.html&media=https://lh3.googleusercontent.com/blogger_img_proxy/AEn0k_tU77-xKM71FJ3D98ZYPaCiZM6GaeQ-3wYh0RJA_K1YLsIKeVbfxAcG_ZPjSt_MVMOxfIzehR2jRqQOboxpZLy2SetfyNPS7Ryh-3ZOLks-eg5LIXFcqaZm2iYp6OjiXix69fUP&description=Google Develops In-House Arm 'Axion' CPU for Datacenters <p align="center"><a href="https://www.anandtech.com/show/21343/google-develops-inhouse-axion-cpu-for-datacenters"><img src="https://images.anandtech.com/doci/21343/google-axion-678_575px.jpg" alt="" /></a></p><p><p>Google was among the first hyperscalers build custom silicon for its services, starting first with tensor processing units (TPUs) for its AI initiatives, and then <a href="https://www.tomshardware.com/news/intel-replaces-xeons-with-custom-vcus">video transcoding units (VCUs)</a> for the YouTube service. But unlike its industry peers, the company has been slower to adopt custom CPU designs, prefering to stick to off-the-shelf chips from the major CPUs. This is finally changing at Google, with the announcement that the company has developed its own in-house datacenter CPU, the Axion.</p>
<p>Google's Axion processor is based on the <a href="https://www.anandtech.com/show/17575/arm-announces-neoverse-v2-and-e2-the-next-generation-of-arm-server-cpu-cores">Arm Neoverse V2</a> (Arm v9) platform, which is Arm's current-generation design for high-performance server CPUs, and is already employed in other chips such as NVIDIA's Grace and Amazon's Graviton4. Within Google, Axion is aimed at a wide variety of workloads, including web and app servers, data analytics, microservices, and AI training. Google claims that the Axion processors boast up to 50% higher performance and up to 60% better energy efficiency compared to current-generation x86-based processors, as well as offer a 30% higher performance compared to competing Arm-based CPUs for datacenters. Though as is increasingly common for the cryptic cloud side of Google's business, least for now the company isn't specifying what processors they're comparing Axion to in these metrics.</p>
<p>While Google is not disclosing core counts or the full specifications of its Axion CPUs, the company is revealing that they are incorporating their own secret sauce into the silicon in the form of the company's <a href="https://cloud.google.com/titanium?e=48754805&hl=en">Titanium</a> purpose-built microcontrollers. These microcontrollers are designed to handle basic operations like networking and security, as well as offload storage I/O processing to Hyperdisk block storage service. As a result of this offloading, virtually all of the CPU core resources should be available to actual workloads. As for the chip's memory subsystem, Axion uses conventional dual-rank DDR5 memory modules.</p>
<p>"Google's announcement of the new Axion CPU marks a significant milestone in delivering custom silicon that is optimized for Google's infrastructure, and built on our high-performance Arm Neoverse V2 platform," said Rene Haas, CEO of Arm. "Decades of ecosystem investment, combined with Google's ongoing innovation and open-source software contributions ensure the best experience for the workloads that matter most to customers running on Arm everywhere." </p>
<p>Google has previously deployed Arm-based processors for its own services, including BigTable, Spanner, BigQuery, and YouTube Ads and is ready to offer instances based on its Armv9-based Axion CPUs to its customers that can use software developed for Arm architectures.</p>
<p>Sources: <a href="https://cloud.google.com/blog/products/compute/introducing-googles-new-arm-based-cpu">Google</a>, <a href="https://www.wsj.com/tech/google-expands-in-house-chip-efforts-in-costly-ai-battle-3121c852?st=6010gt7v4bee9ve&reflink=desktopwebshare_permalink&s=31">Wall Street Journal</a></p>
</p> CPUs){kind=link}
![](https://web.whatsapp.com/send?text=Google Develops In-House Arm 'Axion' CPU for Datacenters <p align="center"><a href="https://www.anandtech.com/show/21343/google-develops-inhouse-axion-cpu-for-datacenters"><img src="https://images.anandtech.com/doci/21343/google-axion-678_575px.jpg" alt="" /></a></p><p><p>Google was among the first hyperscalers build custom silicon for its services, starting first with tensor processing units (TPUs) for its AI initiatives, and then <a href="https://www.tomshardware.com/news/intel-replaces-xeons-with-custom-vcus">video transcoding units (VCUs)</a> for the YouTube service. But unlike its industry peers, the company has been slower to adopt custom CPU designs, prefering to stick to off-the-shelf chips from the major CPUs. This is finally changing at Google, with the announcement that the company has developed its own in-house datacenter CPU, the Axion.</p>
<p>Google's Axion processor is based on the <a href="https://www.anandtech.com/show/17575/arm-announces-neoverse-v2-and-e2-the-next-generation-of-arm-server-cpu-cores">Arm Neoverse V2</a> (Arm v9) platform, which is Arm's current-generation design for high-performance server CPUs, and is already employed in other chips such as NVIDIA's Grace and Amazon's Graviton4. Within Google, Axion is aimed at a wide variety of workloads, including web and app servers, data analytics, microservices, and AI training. Google claims that the Axion processors boast up to 50% higher performance and up to 60% better energy efficiency compared to current-generation x86-based processors, as well as offer a 30% higher performance compared to competing Arm-based CPUs for datacenters. Though as is increasingly common for the cryptic cloud side of Google's business, least for now the company isn't specifying what processors they're comparing Axion to in these metrics.</p>
<p>While Google is not disclosing core counts or the full specifications of its Axion CPUs, the company is revealing that they are incorporating their own secret sauce into the silicon in the form of the company's <a href="https://cloud.google.com/titanium?e=48754805&hl=en">Titanium</a> purpose-built microcontrollers. These microcontrollers are designed to handle basic operations like networking and security, as well as offload storage I/O processing to Hyperdisk block storage service. As a result of this offloading, virtually all of the CPU core resources should be available to actual workloads. As for the chip's memory subsystem, Axion uses conventional dual-rank DDR5 memory modules.</p>
<p>"Google's announcement of the new Axion CPU marks a significant milestone in delivering custom silicon that is optimized for Google's infrastructure, and built on our high-performance Arm Neoverse V2 platform," said Rene Haas, CEO of Arm. "Decades of ecosystem investment, combined with Google's ongoing innovation and open-source software contributions ensure the best experience for the workloads that matter most to customers running on Arm everywhere." </p>
<p>Google has previously deployed Arm-based processors for its own services, including BigTable, Spanner, BigQuery, and YouTube Ads and is ready to offer instances based on its Armv9-based Axion CPUs to its customers that can use software developed for Arm architectures.</p>
<p>Sources: <a href="https://cloud.google.com/blog/products/compute/introducing-googles-new-arm-based-cpu">Google</a>, <a href="https://www.wsj.com/tech/google-expands-in-house-chip-efforts-in-costly-ai-battle-3121c852?st=6010gt7v4bee9ve&reflink=desktopwebshare_permalink&s=31">Wall Street Journal</a></p>
</p> CPUs | https://compbuddey.blogspot.com/2024/04/google-develops-in-house-arm-axion-cpu_14.html){kind=link}
![](mailto:?subject=Google Develops In-House Arm 'Axion' CPU for Datacenters <p align="center"><a href="https://www.anandtech.com/show/21343/google-develops-inhouse-axion-cpu-for-datacenters"><img src="https://images.anandtech.com/doci/21343/google-axion-678_575px.jpg" alt="" /></a></p><p><p>Google was among the first hyperscalers build custom silicon for its services, starting first with tensor processing units (TPUs) for its AI initiatives, and then <a href="https://www.tomshardware.com/news/intel-replaces-xeons-with-custom-vcus">video transcoding units (VCUs)</a> for the YouTube service. But unlike its industry peers, the company has been slower to adopt custom CPU designs, prefering to stick to off-the-shelf chips from the major CPUs. This is finally changing at Google, with the announcement that the company has developed its own in-house datacenter CPU, the Axion.</p>
<p>Google's Axion processor is based on the <a href="https://www.anandtech.com/show/17575/arm-announces-neoverse-v2-and-e2-the-next-generation-of-arm-server-cpu-cores">Arm Neoverse V2</a> (Arm v9) platform, which is Arm's current-generation design for high-performance server CPUs, and is already employed in other chips such as NVIDIA's Grace and Amazon's Graviton4. Within Google, Axion is aimed at a wide variety of workloads, including web and app servers, data analytics, microservices, and AI training. Google claims that the Axion processors boast up to 50% higher performance and up to 60% better energy efficiency compared to current-generation x86-based processors, as well as offer a 30% higher performance compared to competing Arm-based CPUs for datacenters. Though as is increasingly common for the cryptic cloud side of Google's business, least for now the company isn't specifying what processors they're comparing Axion to in these metrics.</p>
<p>While Google is not disclosing core counts or the full specifications of its Axion CPUs, the company is revealing that they are incorporating their own secret sauce into the silicon in the form of the company's <a href="https://cloud.google.com/titanium?e=48754805&hl=en">Titanium</a> purpose-built microcontrollers. These microcontrollers are designed to handle basic operations like networking and security, as well as offload storage I/O processing to Hyperdisk block storage service. As a result of this offloading, virtually all of the CPU core resources should be available to actual workloads. As for the chip's memory subsystem, Axion uses conventional dual-rank DDR5 memory modules.</p>
<p>"Google's announcement of the new Axion CPU marks a significant milestone in delivering custom silicon that is optimized for Google's infrastructure, and built on our high-performance Arm Neoverse V2 platform," said Rene Haas, CEO of Arm. "Decades of ecosystem investment, combined with Google's ongoing innovation and open-source software contributions ensure the best experience for the workloads that matter most to customers running on Arm everywhere." </p>
<p>Google has previously deployed Arm-based processors for its own services, including BigTable, Spanner, BigQuery, and YouTube Ads and is ready to offer instances based on its Armv9-based Axion CPUs to its customers that can use software developed for Arm architectures.</p>
<p>Sources: <a href="https://cloud.google.com/blog/products/compute/introducing-googles-new-arm-based-cpu">Google</a>, <a href="https://www.wsj.com/tech/google-expands-in-house-chip-efforts-in-costly-ai-battle-3121c852?st=6010gt7v4bee9ve&reflink=desktopwebshare_permalink&s=31">Wall Street Journal</a></p>
</p> CPUs&body=https://compbuddey.blogspot.com/2024/04/google-develops-in-house-arm-axion-cpu_14.html){kind=link}
Update on Intel's Panther Lake at Computex 2024, Intel Powering Up Intel 18A Wafer Next Week 
During the Intel keynote hosted by CEO Pat Gelsinger, he gave the world a glimpse into the Intel Client roadmap until 2026. Meteor Lake launched last year on that roadmap, and Lunar Lake, which we dived into yesterday as Intel disclosed technical details about the upcoming platform. Pat also presented a wafer on stage, Panther Lake, and he gave some additional information about Intel's forthcoming Panther Lake platform, which is expected in 2025.
We covered Intel's initial announcement about the Panther Lake platform last year. It is set to be Intel's first client platform using its Intel 18A node. Aside from once again affirming that things are on track for a 2026 launch, Pat Gelsinger, Intel's CEO, also confirmed that they will be powering on the first 18A wafer for Panther Lake as early as next week.
| Intel CPU Architecture Generations | |||||
| Alder/Raptor Lake | Meteor Lake |
Lunar Lake |
Arrow Lake |
Panther Lake |
|
| P-Core Architecture | Golden Cove/ Raptor Cove |
Redwood Cove | Lion Cove | Lion Cove | Cougar Cove? |
| E-Core Architecture | Gracemont | Crestmont | Skymont | Crestmont? | Darkmont? |
| GPU Architecture | Xe-LP | Xe-LPG | Xe2 | Xe2? | ? |
| NPU Architecture | N/A | NPU 3720 | NPU 4 | ? | ? |
| Active Tiles | 1 (Monolithic) | 4 | 2 | 4? | ? |
| Manufacturing Processes | Intel 7 | Intel 4 + TSMC N6 + TSMC N5 | TSMC N3B + TSMC N6 | Intel 20A + More | Intel 18A + ? |
| Segment | Mobile + Desktop | Mobile | LP Mobile | HP Mobile + Desktop | Mobile? |
| Release Date (OEM) | Q4'2021 | Q4'2023 | Q3'2024 | Q4'2024 | 2025 |
One element to consider from last year is that Lunar Lake is built using TSMC, with the Lunar Lake compute tile with Xe2-LPG graphics on TSMC N3B, and the I/O tile on TSMC N6. Pat confirmed on stage that Panther Lake will be on Intel 18A. Still, he didn't confirm whether the chip will be made purely at Intel, or a mix between Intel and external foundries (ala Meteor Lake). Intel has also yet to confirm the CPU cores to be used, but from what our sources tell us, it sounds like it will be the new Cougar Cove and Darkmont cores.
As we head into the second half of 2024 and after Lunar Lake launches, Intel may divulge more information, including the architectural advancements Panther Lake is expected to bring. Until then, we will have to wait and see.
CPUs
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